Sept. 2, 2026

Physical Design, VLSI - New College Grad 2027

NVIDIA Multiple locations

RTL DFT

1mo

Design Engineer - STA

Broadcom Fort Collins, Colorado

ASIC STA

1mo

Senior Serdes System Design Engineer/Architect

Broadcom Multiple locations

ASIC RTL

1mo

Senior Digital Design Engineer

Analog Devices Bangalore, India

RTL Digital Design

1mo

Senior Manager, Digital Design Engineering

Analog Devices Shanghai, Shanghai

RTL Digital Design

1mo

System IP RTL Design Lead

Tenstorrent Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Sr. Hardware Design Engineer/Signal Integrity/FPGA

A2e Technologies San Diego, California

FPGA SOC

1mo

SR. FPGA Design Engineer w/Active Clearance

A2e Technologies San Diego, California

VHDL SystemVerilog

1mo

Sr. Firmware Engineer US ONLY

A2e Technologies Reston, Virginia

VHDL SystemVerilog

1mo

FPGA Design & Verification Engineer-US Only

A2e Technologies Remote

Remote SystemVerilog FPGA

1mo

FPGA Digital Design Engineering Intern (Jan 2027) (4-16 months)

Kepler Communications Toronto, California

VHDL Verilog

1mo

Embedded Software Engineering Intern (January 2027) (4 months)

Kepler Communications Toronto, California

VHDL Verilog

1mo

Embedded Software Designer

Kepler Communications Toronto, California

VHDL Verilog

1mo

Sept. 1, 2026

CPU Circuit Design Engineer

Intel Austin, Texas

RTL STA

1mo

Lead Design Engineer, SoC Design

NXP Semiconductors Pune, Maharashtra

Digital Design Verification

1mo

Senior Lead Engineer - STA

NXP Semiconductors Noida, Uttar Pradesh

STA DFT

1mo

Senior/Principal verification Engineer

NXP Semiconductors Hyderabad, Telangana

SystemVerilog RTL

1mo

Linux Software Engineer

NXP Semiconductors Bucharest, Bucharest

VHDL HDL

1mo

SoC Architect

NXP Semiconductors Pune, Maharashtra

RTL SOC

1mo

SOC chip lead

NXP Semiconductors Pune, Maharashtra

RTL DFT

1mo

Senior QA Automation Engineer, ASIC Simulation

NVIDIA Kyiv, Kyiv

ASIC

1mo

Senior Verification Engineer, SoC

NVIDIA Multiple locations

Verilog System Verilog

1mo

DPU Performance Validation Engineer

NVIDIA Tel Aviv, Tel Aviv District

FPGA ASIC

1mo

Senior Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

1mo

GPU Core Pipeline IP Verification Engineer

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Senior Verification Engineer, Switch SoC

NVIDIA Bengaluru, Karnataka

Verilog UVM

1mo

Architect – AI-Powered Performance Verification Automation

NVIDIA Bengaluru, Karnataka

SystemVerilog UVM

1mo

ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog System Verilog

1mo

Compiler Verification Engineer, Compute Performance – GPU

NVIDIA Multiple locations

Verification

1mo

Manager for IO and Mixed Signal Design

Broadcom Singapore, Central Singapore

Static Timing Place and Route

1mo

DFT Engineer

Broadcom San Jose, California

DFT Design for Test

1mo

Senior Digital Design Engineer

CACI Multiple locations

VHDL Verilog

1mo

Manager Digital Engineering 2

Northrop Grumman Baltimore, Maryland

FPGA ASIC

1mo

Senior Design Verification Engineer - TeraWave

Blue Origin Central Texas; Greater Seattle Area; Bay Area, CA

SystemVerilog ASIC

1mo

Principal Emulation & Prototyping Engineer

Blue Origin San Diego, California

Verilog SystemVerilog

1mo

Sr Principal Verification Engineer

Analog Devices Bangalore, India

Verilog SystemVerilog

1mo

Video Codec Digital Circuit Design Engineer

Qualcomm Taipei, Taipei

ASIC RTL

1mo

#Systems SoC Test Engineer

Qualcomm San Diego, California

SOC

1mo

Senior Director SoC Architecture - AI Accelerators (Multiple Locations)

Qualcomm Multiple locations

ASIC Verification

1mo

Senior SoC Platform Software Engineer

Qualcomm Zhubei City, Hsinchu City, Taiwan

SOC

1mo

SoC Thermal Engineer

Qualcomm Bangalore, India

FPGA SOC

1mo

CPU Micro-Architecture and RTL Design Engineer (RISC-V)

Qualcomm Multiple locations

VHDL Verilog

1mo

AI/ML Logic Design Engineer-Senior

Qualcomm Austin, Texas

SystemVerilog RTL

1mo

FPGA Engineer - Hod HaSharon

Qualcomm Hod HaSharon, Central District

Verilog SystemVerilog

1mo

CAD Engineer on ML/AI for Design Verification

Qualcomm San Diego, California

ASIC Verification

1mo

CPU Server Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

1mo

SoC Power Validation Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

Graphics Modelling Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1mo

GPU Design Verification Engineer

Qualcomm Markham, Ontario

VHDL Verilog

1mo

GPU Design Verification Engineer

Qualcomm Multiple locations

VHDL Verilog

1mo