today

Integrated Circuits Intern

Draper Cambridge, Massachusetts

Verilog System Verilog

18h

Electrical Engineering Intern, Summer 2027

BAE Systems Multiple locations

FPGA Digital Design

18h

SoC Integration and Design Engineer

Broadcom Multiple locations

VHDL Verilog

18h

Design Verification - Intern

Marvell Petah-Tikva

Verilog System Verilog

18h

RTL Design - Director

Qualcomm Bangalore, India

FPGA ASIC

18h

DDR Validation Engineer

Qualcomm Tijuana, Baja California

FPGA ASIC

18h

Verification Software Engineer

Qualcomm San Diego, California

FPGA ASIC

18h

VLSI IP Characterization Engineer, Senior to Staff

Qualcomm Hsinchu City, Taiwan

Verilog System Verilog

18h

Framework Developer Engineer

Qualcomm Tijuana, Baja California

VHDL Verilog

18h

ASICS Design Verification Engineer - Multiple levels

Qualcomm Vancouver, British Columbia

VHDL Verilog

18h

AICS Design Verification Engineer- Multiple levels

Qualcomm Vancouver, British Columbia

VHDL Verilog

18h

NOC DV Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

18h

Physical Design Engineer, Senior

Qualcomm Hyderabad, Telangana

ASIC RTL

18h

Physical Design Engineer, Lead

Qualcomm Hyderabad, Telangana

ASIC RTL

18h

Physical Design Engineer, Senior

Qualcomm Hyderabad, Telangana

ASIC RTL

18h

SOC Design Implementation Engineer

Qualcomm Hyderabad, Telangana

FPGA RTL

18h

Physical Design Engineer, Senior Lead

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

Physical Design Engineer, Senior Lead

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

Physical Design Engineer, Senior Lead

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

Physical Design Engineer, Senior Lead

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform)

Qualcomm San Diego, California

ASIC Digital Design

18h

SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff

Qualcomm Tijuana, Baja California

ASIC Digital Design

18h

SOC Clock & Power Management Validation Engineer, Staff

Qualcomm Tijuana, Baja California

Verilog System Verilog

18h

DDR Validation Engineer, Staff

Qualcomm Tijuana, Baja California

FPGA ASIC

18h

Digital SOC Product Development and Test Engineer, Senior / Staff (Test Program Owner)

Qualcomm Singapore, Central Singapore

DFT SOC

18h

Graphics System/Silicon Validation Engineer

Qualcomm San Diego, California

ASIC DFT

18h

System Validation Engineer (AI Accelerator Platform)

Qualcomm Tijuana, Baja California

VHDL Verilog

18h

SVE Validation framework and QA Engineer

Qualcomm Tijuana, Baja California

VHDL Verilog

18h

DDR PHY Senior Lead Digital Design Engineer

Qualcomm Bangalore, India

Verilog SystemVerilog

18h

DFT Engineer

Qualcomm Noida, Uttar Pradesh

FPGA RTL

18h

Sr Engineer - DFT

Qualcomm Noida, Uttar Pradesh

FPGA RTL

18h

Physical Design Engineer, Lead Engineer Senior

Qualcomm Hyderabad, Telangana

ASIC STA

18h

Physical Design Engineer, Senior Lead

Qualcomm Hyderabad, Telangana

FPGA ASIC

18h

Senior Digital Design

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

19h

Sr. Avionics Systems Engineer — Advanced Technology & Architecture

Blue Origin Greater Seattle Area

FPGA Digital Design

19h

Sr ASIC Design Engineer - TeraWave

Blue Origin Multiple locations

VHDL Verilog

19h

Space Vehicle Verification and Validation Lead - Blue Ring

Blue Origin Multiple locations

Verification

19h

Senior Electrical Power Engineer, RF Payloads - TeraWave

Blue Origin Cupertino, California

FPGA DFT

19h

Senior Design Engineer

Silicon Labs Singapore, Central Singapore

RTL SOC

19h

Senior Software Verification Engineer

NVIDIA Warsaw, Masovian Voivodeship

Verification

19h

2027 Software Digital Intern - Rolling Meadows IL

Northrop Grumman Rolling Meadows, Illinois

VHDL Verilog

19h

Staff FPGA Digital Engineer - 5

Northrop Grumman Chandler, Arizona

VHDL Verilog

19h

Technical Staff - Design Engineering

Microchip Technology Bangalore, India

Verilog SystemVerilog

19h

Senior Manager - Design Engineering

Microchip Technology Bangalore, India

ASIC RTL

19h

Mid-level Physical Design Engineer CPU

Intel Hillsboro, Oregon

RTL STA

20h

AI SOC Power Delivery Pathfinding PhD Intern

Intel Hillsboro, Oregon

SOC Verification

20h

Engineer, Digital Design Engineering

Analog Devices Valencia, Valencia

Verilog SystemVerilog

20h

Modeling Design, Staff Engineer

Lattice Semiconductor Multiple locations

VHDL Verilog

20h

STAFF ENGINEER, ASIC VALIDATION

Micron Hyderabad, Telangana

SOC Verification

20h

Interface Design Architect, HBM - DMTS

Micron Richardson, Texas

Verilog SystemVerilog

20h