106 open FPGA & RTL jobs at SiFive
106 open logic design roles at SiFive.
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Senior CPU Formal Verification Engineer
Senior CPU Design Verification Engineer
Distinguished Formal Verification Architect
Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification)
Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)
Staff Engineer Formal(IOMMU-N)
Staff Formal Verification Engineer
Principal Field Application Engineer
Staff Design Verification Engineer – Coherent Interconnect (CHI)
System Validation Engineer (New Grads)
Staff Design Verification Engineer – High Performance CPU Core
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