yesterday

Verification Software Engineer

Qualcomm San Diego, California

FPGA RTL

1d

Physical Design Engineer- Staff to Sr. Staff

Qualcomm Austin, Texas

ASIC RTL

1d

Principal Engineer / Manager - Cellular Technologies

Qualcomm San Diego, California

Design for Test SOC

1d

Principal/Sr. Principal Digital Design Engineer

Northrop Grumman Rolling Meadows, Illinois

FPGA Digital Design

1d

Principal / Sr. Principal PCB Layout Designer

Northrop Grumman Woodland Hills, California

DFT Design for Test

1d

Senior FPGA Developer

Philips Suzhou

VHDL Verilog

1d

AMS Verification Intern - Master's Degree

Marvell Singapore, Central Singapore

Verilog Verification

1d

Entry Level Hardware Engineer - Electrical/Power/Firmware/RF (Hybrid)

BAE Systems Multiple locations

VHDL FPGA

1d

Staff Engineer Design

Micron Hyderabad, Telangana

Verilog RTL

1d

Design Verification Engineer

Micron Jalisco, Chiapas

Verilog SystemVerilog

1d

Design Lead (HBM/Advanced Memory Design)

Micron Richardson, Texas

Verilog SystemVerilog

1d

Design Lead (HBM/Advanced Memory Design)

Micron Richardson, Texas

Verilog SystemVerilog

1d

Staff Engineer, SSD Hardware PCIE

Micron Longmont-MAX- Office, CO

FPGA ASIC

1d

New College Grad - HBM SoC Design Engineer/Architect

Micron Multiple locations

VHDL Verilog

1d

Senior Electronics Test Engineer

CesiumAstro Westminster, Colorado

DFT Design for Test

1d

Technical Program Manager SOC & Digital Design

Tenstorrent Tokyo, Tokyo

DFT SOC

1d

Design Verification Intern

Ambiq Micro, Inc. Singapore, Central Singapore

Verilog SystemVerilog

1d

Senior Software Engineer (AOSP/Qualcomm SoC Connectivity)

Anduril Bellevue, Washington

SOC

1d

Sept. 29, 2026

Verification Engineer

Philips Haifa, Haifa District

Verification

2d

IC Design Engineer

Broadcom Multiple locations

Verilog SystemVerilog

2d

Physical Design Engineer

Broadcom Multiple locations

RTL STA

2d

Physical Design Engineer

Broadcom Multiple locations

RTL STA

2d

Physical Design Engineer

Broadcom Multiple locations

RTL STA

2d

Physical Design Engineer

Broadcom Multiple locations

RTL STA

2d

Formal Verification Engineer

Intel Bangalore, India

Verilog System Verilog

2d

Graduate Talent (ISCP SoC Front End Team)

Intel Penang, Malaysia

Verilog SystemVerilog

2d

Graduate Talent (ISCP SoC Front End Team)

Intel Penang, Malaysia

VHDL Verilog

2d

• AI/ML CAD Engineer, RTL & Design Verification

Intel Multiple locations

Verilog SystemVerilog

2d

IP Design Verification Engineer

Intel Multiple locations

Verilog SystemVerilog

2d

AI GPU Cache Designer

Intel Multiple locations

Verilog SystemVerilog

2d

Senior Embedded Systems Engineer - TeraWave

Blue Origin Multiple locations

VHDL Verilog

2d

Sr. Solid-State Power Amplifier (SSPA) Responsible Engineer - Lunar Permanence

Blue Origin Multiple locations

FPGA ASIC

2d

Mixed Signal Verification Lead Engineer

NXP Semiconductors Pune, Maharashtra

Verilog System Verilog

2d

Senior Principal Digital Design Engineer

NXP Semiconductors Sophia-Antipolis (Valbonne)

Verilog SystemVerilog

2d

Test Engineer – NPI Development

NXP Semiconductors Kuala Lumpur, Kuala Lumpur

RTL DFT

2d

Senior Engineer - Design Verification

SiFive Ahmedabad, Gujarat

SystemVerilog FPGA

2d

Senior Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

2d

Senior ASIC Design Engineer, GPU Core Pipeline IP

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

2d

System Security Software Engineer

NVIDIA Pune, Maharashtra

FPGA SOC

2d

Senior System Software Engineer - GPU and SOC

NVIDIA Multiple locations

SOC

2d

Senior System Software Engineer, NVLink Fusion

NVIDIA Multiple locations

FPGA ASIC

2d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

2d

ASIC Verification Engineer, Memory Management - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

2d

ASIC Design Engineer - New College Grad 2027

NVIDIA Santa Clara, California

Verilog ASIC

2d

Senior Build and Release Methodology Engineer

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

2d

Senior DFT Verification Engineer

NVIDIA Multiple locations

RTL DFT

2d

DFT Verification Engineer

NVIDIA Multiple locations

RTL DFT

2d

Senior DFT Verification Engineer

NVIDIA Multiple locations

RTL DFT

2d

Principal Engineer - Design

Microchip Technology Bangalore, India

SystemVerilog ASIC

2d

Senior Manager, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

2d