Sept. 3, 2026

Senior Digital Design Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

VHDL Verilog

29d

Sept. 2, 2026

ASIC / NoC Power and Solutions Senior/Staff Engineer - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

1mo

Staff Engineer, Silicon & Data Automation Systems (Design, DFT, Diagnostics, Yield)

Qualcomm Bangalore, India

DFT

1mo

CAD and PPA Methodology Engineer

Qualcomm San Diego, California

Verilog System Verilog

1mo

Physical Design Engineer (Engineer up to Principal Level)

Qualcomm Multiple locations

ASIC RTL

1mo

CPU-Core RTL Director

Qualcomm Multiple locations

SystemVerilog RTL

1mo

Heterogeneous Integration Physical Design Engineer, Staff

Qualcomm Hsinchu City, Taiwan

ASIC SOC

1mo

Director of Engineering for ML hardware design & Architecture

Qualcomm San Diego, California

Verilog SystemVerilog

1mo

NPU/AI Processor Synthesis Staff/ Sr Staff/ Technical Lead

Qualcomm Bangalore, India

ASIC RTL

1mo

Staff CPU Power Management Firmware Developer - Limits Management

Qualcomm Hyderabad, Telangana

FPGA SOC

1mo

STCO Methodology & Framework Technologist, up to Staff

Qualcomm Hsinchu City, Taiwan

ASIC SOC

1mo

Memory Yield Engineer, Staff

Qualcomm Hsinchu City, Taiwan

ASIC SOC

1mo

CPU RTL Methodology Engineer

Qualcomm Multiple locations

Verilog SystemVerilog

1mo

CPU Systems Architect – Senior Level

Qualcomm Santa Clara, California

RTL Logic Design

1mo

CPU Verification Engineer, Up to Staff Level

Qualcomm Hsinchu City, Taiwan

VHDL Verilog

1mo

Staff CPU Power Management Firmware Developer - Performance Management

Qualcomm Hyderabad, Telangana

FPGA SOC

1mo

Staff Engineer, Physical Design/Implementation

Qualcomm Toronto, Ontario

ASIC Synthesis

1mo

Engineer

Qualcomm Markham, Ontario

Verilog SystemVerilog

1mo

Core CPU Physical Design Engineer (Lead/Staff/Sr Staff)

Qualcomm Bangalore, India

FPGA RTL

1mo

CPU RTL Power Engineer (Sr Staff/Principal)

Qualcomm Bangalore, India

FPGA ASIC

1mo

SOC Architecture

Qualcomm San Diego, California

ASIC SOC

1mo

Senior Staff Verification Engineer - Video

Qualcomm Bangalore, India

SystemVerilog FPGA

1mo

CPU RTL Power Engineer

Qualcomm Austin, Texas

VHDL Verilog

1mo

RTL Design (SOC) Engineer-Staff

Qualcomm Bangalore, India

Synthesis SOC

1mo

Staff Engineer – SOC Design Verification

Qualcomm Noida, Uttar Pradesh

Verilog System Verilog

1mo

Microcontroller Sub-System Verification Engineer / Senior Engineer, - Cork, Ireland

Qualcomm Cork, Munster

SystemVerilog ASIC

1mo

CPU Physical Design Engineer, San Diego

Qualcomm San Diego, California

Verilog RTL

1mo

ASICS Design Verification Engineer-Senior

Qualcomm San Diego, California

VHDL Verilog

1mo

Sr. Staff Verification Engineer- LoRa

Semtech Hyderabad, Telangana

SystemVerilog RTL

1mo

Staff Analog IC Engineer

Semtech Hyderabad, Telangana

Verilog SystemVerilog

1mo

Senior Engineer II - CAD (Physical Verification)

Microchip Technology Chandler, Arizona

Verification

1mo

Advanced Packaging Design Verification & Physical Validation Engineer

Marvell Burlington, Vermont

Verification

1mo

Senior Design Engineer - Post Silicon Validation

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Senior Manager, QA Engineering – Hardware & Firmware

Lattice Semiconductor Pune, Maharashtra

SystemVerilog FPGA

1mo

Design Verification Eng 2(IP/SoC)

Lattice Semiconductor Multiple locations

Verilog System Verilog

1mo

Sr. Memory Designer

Lattice Semiconductor San Jose, California

SystemVerilog FPGA

1mo

Sr. Systems Engineer — Lunar Human Landing System (HLS)

Blue Origin Multiple locations

HLS Verification

1mo

Senior Digital ASIC Architect

Draper Cambridge, Massachusetts

Verilog System Verilog

1mo

Senior Principal Analog Engineer -Power Management

NXP Semiconductors Hsinchu

Verilog Digital Design

1mo

AI/ML driven ASIC Design and Implementation Automation Engineer

NXP Semiconductors San Diego, California

VHDL Verilog

1mo

Principal Digital Verification Engineer (mfd)

NXP Semiconductors Gratkorn

VHDL Verilog

1mo

Principal SoC Design Lead

NXP Semiconductors Toulouse, Occitanie

SOC

1mo

DFT Design Engineer

Intel Bangalore, India

RTL DFT

1mo

SoC Design Verification Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

Design Automation Engineer - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

1mo

Product Development/DFX Lead - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

1mo

Senior Design Verification Engineer - Neuromorphic Computing

Intel Multiple locations

ASIC RTL

1mo

ASIC Design Engineer - Pixel IP ANE

Apple Sunnyvale, United States

RTL Static Timing

1mo

ASIC Design Engineer - Pixel IP ANE

Apple Sunnyvale, United States

RTL Static Timing

1mo

Design Verification Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

SystemVerilog RTL

1mo