today

New College Grad - ENG, HIG HBM PSE Design Validation

Micron Boise, Idaho

VHDL Verilog

18h

New College Grad - ENG, HIG HBM PSE Design Validation

Micron Boise, Idaho

VHDL Verilog

18h

MTS SoC DFT Engineer, HBM

Micron Multiple locations

ASIC RTL

18h

STAFF ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

18h

ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

18h

Design Verification Engineer

Micron Jalisco, Chiapas

Verilog SystemVerilog

18h

ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

18h

Principal Engineer, ASIC Physical Design

Micron Hyderabad, Telangana

ASIC STA

18h

Engineer, EDG Verification

Micron Vimercate, Lombardy

DFT Verification

18h

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

18h

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

Verilog System Verilog

18h

Sr. ASIC Design Engineer (Silicon Engineering)

SpaceX Irvine, California

Verilog System Verilog

18h

RF Silicon Software Engineer (RFIC Engineering)

SpaceX Redmond, Washington

SystemVerilog FPGA

18h

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX Irvine, California

VHDL Verilog

18h

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX Redmond, Washington

VHDL Verilog

18h

Senior Product, Test and Yield Enhancement Engineer - Taiwan

Cerebras Systems Sunnyvale, California

Remote ASIC DFT

18h

Staff FPGA Engineer - RF Comm Systems/Simulink

Anduril Costa Mesa, California

VHDL Verilog

18h

Senior PCB Design Engineer, Intelligence Systems

Anduril Reston, Virginia

FPGA Digital Design

18h

yesterday

DFT Engineer (RDSS Intern) - 2027

NVIDIA Multiple locations

RTL DFT

1d

Senior Manager, Silicon Speed Productization — Silicon Co-Design Group

NVIDIA Santa Clara, California

Digital Design Static Timing

1d

Senior Chip Design Verification Engineer

NVIDIA Multiple locations

ASIC RTL

1d

Senior Technical Program Manager – DFX Software Methodology

NVIDIA Santa Clara, California

ASIC RTL

1d

PhD Research Intern, AI Accelerator Design and VLSI - 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

1d

Sr Silicon Bring-Up and Integration Engineer

Blue Origin Cupertino, California

FPGA ASIC

1d

Principal VLSI Engineer

HPE Juniper Networks Bengaluru, Karnataka

FPGA Logic Design

1d

Digital Engineer

Silicon Labs Singapore, Central Singapore

Digital Design SOC

1d

Test Engineer (ATE)

Broadcom San Jose, California

ASIC DFT

1d

Senior Field Applications Engineer

Lattice Semiconductor China - Remote

VHDL Verilog

1d

Physical Design Methodology Lead

NXP Semiconductors Noida, Uttar Pradesh

ASIC RTL

1d

Principal Analog IP Design Lead - MCU

NXP Semiconductors Catania, Sicily

Digital Design DFT

1d

Engineering Manager III – Tactical Electronics FPGA Development

BAE Systems Westminster, Colorado

VHDL Verilog

1d

GPU Logic Design Engineer

Intel Multiple locations

Verilog System Verilog

1d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1d

Analog Circuit Design Engineer

Intel Bangalore, India

Verilog SOC

1d

Emulation Engineer

Intel Virtual India

Verilog RTL

1d

Design Verification Engineer II

Silicon Labs Singapore, Central Singapore

SystemVerilog RTL

1d

Engineer II- Design

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1d

Principle Engineer - CAD (Physical Verification)

Microchip Technology Multiple locations

Verification

1d

Director, Product Management - Camera and Vision SoCs

Qualcomm Canada - Remote, Canada

SOC

1d

Sr. Staff Engineer - Verification & Validation Lead

Qualcomm Novi, Michigan

Verification

1d

Processor ASIC RTL Design Engineer

Qualcomm San Diego, California

ASIC RTL

1d

Physical Design Staff Engineer

Qualcomm Noida, Uttar Pradesh

FPGA STA

1d

Senior Lead Physical Design Engineer

Qualcomm Noida, Uttar Pradesh

FPGA STA

1d

Senior Lead Physical Design Engineer

Qualcomm Noida, Uttar Pradesh

FPGA STA

1d

SOC RTL Design - Senior Engineer

Qualcomm Bangalore, India

ASIC RTL

1d

Sr Engineer - HW Board design

Qualcomm Bangalore, India

FPGA ASIC

1d

RF System Level Test (SLT) Engineer, Senior

Qualcomm Hsinchu City, Taiwan

FPGA SOC

1d

CPU Design Verification - Sr Engineer

Qualcomm Bangalore, India

Verilog System Verilog

1d

GPU Systems Validation Engineer, Staff - Cork, Ireland

Qualcomm Cork, Munster

ASIC DFT

1d

Modem HW Design Engineer – AI Driven Next Gen Modem Hardware Development

Qualcomm San Diego, California

Verilog SystemVerilog

1d