FPGA Engineer

About the Team

The Battlespace Awareness (BA) Radar team develops state-of-the-art radar systems, deployed to tackle the most significant security challenges of America and its allies. Working across hardware, software, and firmware; in both the RF and digital domains; the team delivers radar architectures that enable advanced surveillance, reconnaissance, and targeting in the contemporary and future battlespace. The Radar team is responsible for all aspects of radar system development; from concepts and architectures through to fielding and sustainment. In this role, you will work closely with an interdisciplinary technical team to define FPGA designs, determine solutions, build prototypes, perform testing, and mature the prototypes into products.

About the Job

We are looking for an FPGA Engineer to join our growing team in Fort Collins, CO. You will develop and verify FPGA designs that control radar hardware, move high-rate sensor data, and support real-time signal processing. Working alongside experienced FPGA, software, algorithms, and electrical engineers, you will take features from requirements and simulation through timing closure, board bring-up, and product integration.

The role includes RTL development, data acquisition and streaming interfaces, FPGA/processor integration, and improvements to shared designs and verification tools. Radar and DSP experience are valuable but not required; you will pick up the radar-specific concepts on the job.

Our stack: Altera Quartus Pro is our primary flow (Agilex and MAX10 devices), with Platform Designer, Tcl-scripted builds, SignalTap, Nios-V soft processors running C/FreeRTOS, Questa and Verilator simulation with cocotb, and Docker/CircleCI automation. AMD/Xilinx devices are used elsewhere in the radar portfolio using the Vivado toolchain.

What You'll Do

• Design, implement, and verify FPGA modules in SystemVerilog, Verilog, or VHDL for radar control, data acquisition, and real-time processing.
• Build and integrate streaming datapaths, FIFOs, register interfaces, memory access, and FPGA-to-processor communications.
• Develop reliable clocking, reset sequencing, and clock-domain crossings; write and review timing constraints and close timing on supported hardware.
• Work with software and electrical engineers to bring up boards and debug failures across RTL, firmware, interfaces, and hardware.
• Improve throughput, latency, and resource use through pipelining, buffering, and data-movement improvements, with measured results.
• Build self-checking simulations and regression tests that exercise normal operation, backpressure, resets, and error conditions.
• Integrate vendor and third-party IP, and help turn reusable modules into shared FPGA building blocks across radar products.
• Improve scripted build and verification workflows, maintain clear design documentation, and support lab and field integration.

Required Qualifications

• Bachelor's degree in electrical engineering, electronics engineering, computer engineering, or a related field, or 4+ years of directly relevant professional FPGA experience in place of the degree.
• At least 2 years of professional FPGA or RTL development experience (as an employee or contractor), including hands-on work on an FPGA design that reached hardware.
• Proficiency in SystemVerilog, Verilog, or VHDL, with a sound understanding of synchronous digital design.
• Experience taking an FPGA design through simulation, synthesis, implementation, and hardware testing.
• Working knowledge of timing constraints, timing closure, clock-domain crossings, reset behavior, and FPGA resource trade-offs.
• Experience writing self-checking tests and diagnosing problems using simulation results, waveforms, implementation reports, or hardware instrumentation.
• Hands-on experience with Altera Quartus (preferred) or a comparable FPGA toolchain such as AMD Vivado.
• Ability to use Git and a Linux development environment.
• Basic Tcl or Python scripting for FPGA build and test automation, and C for firmware, drivers, or hardware-debug tasks.
• Ability to own a defined engineering task, communicate progress and blockers, and work effectively across software and hardware teams.
• Must be able to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications

Preferred items are not screening criteria; no single item is required.

• Experience with Altera Agilex or other FPGA SoC platforms, and with Platform Designer (Qsys).
• Familiarity with high-speed interfaces such as PCIe, Ethernet (SGMII/RGMII), direct-RF or other high-speed transceivers, LVDS, or optical links, and with DDR memory, DMA, or AXI/Avalon buses.
• Experience with embedded processors (such as Nios II/V or RISC-V), memory-mapped interfaces, interrupts, or low-level C/C++ firmware for bring-up and test.
• Experience with Linux device drivers or host-to-FPGA interfaces.
• DSP implementation experience, including filtering, FFTs, rate conversion, fixed-point arithmetic, or radar/software-defined-radio processing.
• Experience with high-level synthesis using C/C++ or SYCL (such as Intel oneAPI) for DSP kernels, including checking the generated hardware's timing and resource use.
• Experience with Python-based verification (cocotb, pyuvm), SystemVerilog assertions, UVM, or equivalent methods.
• Experience with automated FPGA builds, regression testing, and continuous integration.
• Familiarity with RF test equipment, mixed-signal systems, or lab and field testing of physical products.