49 open FPGA & RTL jobs at Marvell

49 open logic design roles at Marvell.

ASIC jobs DFT jobs FPGA jobs RTL jobs SOC jobs STA jobs SystemVerilog jobs UVM jobs Verification jobs Verilog jobs Arizona California Central Singapore Ontario

Design Verification - Intern

Marvell Petah-Tikva

Verilog System Verilog

16h

AMS Verification Intern - Master's Degree

Marvell Singapore, Central Singapore

Verilog Verification

1d

Principle DFT Engineer

Marvell Bangalore, India

RTL Logic Design

2d

Senior Staff CAD Engineer

Marvell Santa Clara, California

STA Synthesis

2d

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Santa Clara, California

SystemVerilog FPGA

2d

Engineering IP Program Manager, Sr. Principal

Marvell Multiple locations

ASIC Design for Test

5d

Design Verification Intern

Marvell Petah-Tikva; IL - Yokneam

Verilog SystemVerilog

6d

Physical design CAD engineer

Marvell Yokneam; Petah-Tikva

ASIC RTL

6d

Data Center Silicon Hardware Engineering Intern - BS - 2027 Co-Op

Marvell Multiple locations

Verilog SystemVerilog

6d

Digital IC Design Intern

Marvell IL - Petah Tikva

RTL Logic Design

7d

Security Verification/Validation Engineer Intern, BS - Summer 2027

Marvell Chandler, Arizona

Verilog System Verilog

7d

Senior Staff Engineer, Multi-die 3DIC

Marvell Santa Clara, California

ASIC RTL

8d

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