Aug. 20, 2026

Principal Electrical Engineer (Sign On Bonus Available)

BAE Systems Austin, Texas

VHDL FPGA

1mo

Staff Physical Design Engineer

Silicon Labs Hyderabad, Telangana

ASIC RTL

1mo

Director AI/ML Driven ASIC Design and Implementation Automation

NXP Semiconductors Multiple locations

VHDL Verilog

1mo

Staff Design Evaluation Engineer

Analog Devices Limerick, Ireland

DFT Design for Test

1mo

Associate Digital Design Engineer

Analog Devices San Jose, California

Verilog SystemVerilog

1mo

ASIC Design and Integration Engineer – Silicon Security

Apple Cupertino, California

Verilog SystemVerilog

1mo

Sr. PCB Designer (Starship)

SpaceX Hawthorne, California

FPGA Digital Design

1mo

PCB Designer (Starship)

SpaceX Hawthorne, California

FPGA Digital Design

1mo

Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor San Jose, California

Verilog System Verilog

1mo

Senior Physical Design Engineer

Samsung Semiconductor San Jose, California

ASIC RTL

1mo

Senior Emulation Engineer

Samsung Semiconductor San Jose, California

Verilog SystemVerilog

1mo

FPGA Verification Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

SystemVerilog FPGA

1mo

Digital Design Engineer, Air Dominance and Strike

Anduril Costa Mesa, California

VHDL Verilog

1mo

Staff Analog Design Engineer, SerDes Clocking

d-Matrix Multiple locations

Remote Verilog Synthesis

1mo

Aug. 18, 2026

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

1mo

Physical Design STA CAD Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Static Timing

1mo

Microelectronics Integration and Test Engineer

Draper Cambridge, Massachusetts

ASIC Design for Test

1mo

Graduate FPGA Engineer (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

1mo

FPGA Internship (2027 Start)

Optiver Amsterdam, North Holland

VHDL Verilog

1mo

Senior NVM Digital Designer

Mythic AI Palo Alto, California

Verilog SystemVerilog

1mo

Senior Mixed Signal / Memory Circuit Designer

Mythic AI Palo Alto, California

Verilog System Verilog

1mo

Software Engineer - FPGA-Accelerated RTL Simulation

SiFive Berkeley, California

FPGA ASIC

1mo

Aug. 17, 2026

DSP Firmware Engineer

Marvell Córdoba, Córdoba

Verilog SystemVerilog

1mo

Principal ATE Test Engineer (Optical Module)

Marvell Santa Clara, California

ASIC DFT

1mo

Physical Design Intern

Marvell Córdoba, Córdoba

ASIC Static Timing

1mo

Digital IC Design/Verification Engineer

Marvell Córdoba, Córdoba

VHDL Verilog

1mo

Post Silicon Validation Engineer

Marvell Córdoba, Córdoba

Verilog System Verilog

1mo

Digital IC Design Junior Engineer

Marvell Córdoba, Córdoba

VHDL Verilog

1mo

Forward Error Correction Engineer

Marvell Córdoba, Córdoba

Verilog SystemVerilog

1mo

Forward Error Correction Intern

Marvell Córdoba, Córdoba

Verilog SystemVerilog

1mo

Senior Principal Digital IC Design Engineer

Marvell Santa Clara, California

Verilog SystemVerilog

1mo

Principal Board Product Engineer

Marvell Multiple locations

ASIC Digital Design

1mo

Architecture ASIC Engineer

Marvell Córdoba, Córdoba

ASIC Verification

1mo

Senior Staff Physical Verification CAD engineer

Marvell Santa Clara, California

RTL Place and Route

1mo

Senior Staff Physical Verification CAD Engineer

Marvell Singapore, Central Singapore

RTL Place and Route

1mo

Principal, IC Digital Design Engineer

Marvell Irvine, California

SystemVerilog FPGA

1mo

Digital IC Design Engineer

Marvell Córdoba, Córdoba

Verilog SystemVerilog

1mo

Senior Staff Engineer, Firmware Engineering

Marvell Santa Clara, California

Verilog FPGA

1mo

Principal Engineer, Design Verification

Marvell Ho Chi Minh City, Hồ Chí Minh

SystemVerilog ASIC

1mo

Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Marvell Santa Clara, California

ASIC RTL

1mo

Design Engineer

Broadcom Fort Collins, Colorado

ASIC RTL

1mo

ASIC Design Engineer

Broadcom Irvine, California

ASIC Place and Route

1mo

ASIC Design Engineer

Broadcom Irvine, California

ASIC Place and Route

1mo

Silicon Design and Validation Engineer

Broadcom San Jose, California

ASIC IP Design

1mo

ASIC Implementation Engineer

Broadcom San Jose, California

ASIC RTL

1mo

R&D Engineer IC Design

Broadcom San Jose, California

Verilog SystemVerilog

1mo

R&D Engineer IC Design

Broadcom San Jose, California

Verilog SystemVerilog

1mo

Hardware Engineer

Broadcom Irvine, California

Digital Design IP Design

1mo

PCIe design Architect

Broadcom IND-Bangalore Electronic City - S1

ASIC RTL

1mo

Design Verification Engineer

Broadcom San Jose, California

Verilog SystemVerilog

1mo