Aug. 21, 2026

Lunar HLS Manufacturing Chief of Staff

Blue Origin Space Coast, Florida

1mo

Principal Modem PHY IP Design Verification Engineer - Terawave

Blue Origin San Diego, California

SystemVerilog FPGA

1mo

Senior ASIC Design Verification Engineer - Terawave

Blue Origin Los Angeles, California

Verilog System Verilog

1mo

Senior Embedded Software Engineer - TeraWave Customer Terminals

Blue Origin Greater Seattle Area; Bay Area, CA

FPGA SOC

1mo

Aug. 20, 2026

Silicon Validation Engineer

MatX Multiple locations

Remote SystemVerilog RTL

1mo

Senior SoC Power Analysis & Optimization Engineer

MatX Multiple locations

Remote Verilog SystemVerilog

1mo

Design Verification Engineer

MatX Multiple locations

Remote SystemVerilog UVM

1mo

BMC Firmware Engineer

MatX Multiple locations

FPGA ASIC

1mo

System Software Engineer, Linux Kernel and Device Drivers

MatX Multiple locations

FPGA RTL

1mo

Micro-Architect and RTL Designer

MatX Multiple locations

Remote SystemVerilog ASIC

1mo

SOC Integration Engineer

MatX Multiple locations

SystemVerilog RTL

1mo

Emulation Engineer

MatX Multiple locations

Remote Verilog SystemVerilog

1mo

SOC Micro-Architect and RTL Designer

MatX Multiple locations

Remote SystemVerilog ASIC

1mo

Formal Verification Engineer

MatX Multiple locations

Remote RTL HDL

1mo

Rust SW-Silicon Co-verification Engineer

MatX Multiple locations

Remote FPGA Verification

1mo

Silicon Design-for-Test (DFT) Engineer

MatX Multiple locations

Remote DFT Design for Test

1mo

ASIC/SOC CAD Engineer

MatX Multiple locations

Remote ASIC RTL

1mo

ASIC/SOC Silicon Physical Design Engineer

MatX Multiple locations

Remote ASIC RTL

1mo

SoC Design Verification Engineer

MatX Multiple locations

Remote SystemVerilog UVM

1mo

Senior VLSI Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

1mo

Senior ASIC Verification Engineer - HSIO

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

CPU Design Methodology Engineer

NVIDIA Multiple locations

Verilog System Verilog

1mo

System Software Engineer – GPU and SOC (2027 RDSS Intern)

NVIDIA Taipei, Taipei

SOC

1mo

NVIDIA 2027 Internships: Mixed Signal Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware Verification

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware Physical Design / VLSI

NVIDIA Santa Clara, California

Logic Design Digital Design

1mo

NVIDIA 2027 Internships: Hardware Engineering

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware Design for Test (DFT)

NVIDIA Santa Clara, California

Digital Design STA

1mo

NVIDIA 2027 Internships: Hardware ASIC Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Digital Circuit Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Computer Architecture

NVIDIA Santa Clara, California

VHDL Verilog

1mo

CPU Verification Engineer

NVIDIA Bengaluru, Karnataka

Verification

1mo

Senior System Software Engineer - SoC Power

NVIDIA Multiple locations

SOC

1mo

Verification Engineer - PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Senior Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

1mo

Senior ASIC Verification Engineer

NVIDIA Santa Clara, California

ASIC UVM

1mo

Senior ASIC Power Management Micro Architect, Chip Design

NVIDIA Tel Aviv, Tel Aviv District

ASIC RTL

1mo

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verilog System Verilog

1mo

Silicon Validation Engineer

Semtech San Diego, California

VHDL Verilog

1mo

Sr Staff Engineer - Analog IC

Semtech Hyderabad, Telangana

Verilog SystemVerilog

1mo

Digital Signal Processing and System Validation Engineer

Broadcom San Jose, California

Verilog System Verilog

1mo

Foundation IP Memory Verification Engineer

Broadcom Singapore, Central Singapore

DFT Verification

1mo

Foundation IP Memory Verification Engineer

Broadcom Singapore, Central Singapore

DFT Verification

1mo

Foundation IP Design Engineer

Broadcom Singapore, Central Singapore

DFT Verification

1mo

Foundation IP Design Engineer

Broadcom Singapore, Central Singapore

DFT Verification

1mo

IO and Mixed Signal Circuit Design Engineer

Broadcom IND-Bangalore Electronic City - S1

RTL Synthesis

1mo

Senior Field Applications Engineer

Microchip Technology India - Bangalore Sales

VHDL Verilog

1mo

Principal Engineer- Design (FPGA)

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

1mo

Module Development Engineer - RF Test

Intel Phoenix, Arizona

DFT Design for Test

1mo

Senior Staff Foundation IP Engineer (Arithmetic/DSP)

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo