Aug. 29, 2026

Implementation Timing / STA Design Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

Memory Control Design Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

DSP Micro-Architect RTL Engineer

Qualcomm Austin, Texas

ASIC RTL

1mo

GPU PD Engineer (Austin/San Diego)

Qualcomm San Diego, California

Verilog System Verilog

1mo

CPU Synthesis CAD Engineer

Qualcomm Multiple locations

Logic Design Place and Route

1mo

Senior / Staff Product Manager – Camera SoC & Solutions (China)

Qualcomm Guangdong, China

SOC

1mo

Principal SOC Architect, AI Accelerators (Multiple Locations

Qualcomm Multiple Locations

ASIC SOC

1mo

Analog/Mixed Signal ASIC Design Engineer

Qualcomm San Diego, California

VHDL Verilog

1mo

Staff Mixed Signal IC Design Engineer

Qualcomm Hsinchu City, Taiwan

VHDL Verilog

1mo

SOC Design Verification Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

CPU RTL/AI Micro-Architect - AI Development

Qualcomm Multiple locations

VHDL Verilog

1mo

CPU RTL Design - Sr Eng/Lead/Staff/Sr Staff

Qualcomm Bangalore, India

VHDL Verilog

1mo

IP Library Circuit Design Engineer

Qualcomm Hsinchu City, Taiwan

ASIC RTL

1mo

SoC HW Architecture

Qualcomm Multiple locations

RTL SOC

1mo

System IP MicroArchitect

Qualcomm Bangalore, India

Verilog UVM

1mo

Sr Radio Frequency Integrated Circuit (RFIC) Design Engineer

Qualcomm San Diego, California

ASIC SOC

1mo

Design Eng - Modeling

Lattice Semiconductor Manila, Metro Manila

Verilog SystemVerilog

1mo

Senior Staff Design Engineer

Lattice Semiconductor Penang, Malaysia

FPGA ASIC

1mo

System Level Product Development Engineer

NVIDIA Santa Clara, California

ASIC DFT

1mo

Product Development Engineer -- Post-Si Characterization

NVIDIA Santa Clara, California

ASIC Digital Design

1mo

Characterization Product Development Engineer

NVIDIA Santa Clara, California

ASIC Digital Design

1mo

Hardware Engineer

Optiver Austin, Texas

VHDL Verilog

1mo

Aug. 28, 2026

Space Vehicle Verification and Validation Lead - Blue Ring

Blue Origin Multiple locations

Verification

1mo

Senior Avionics Hardware Engineer - Lunar Permanence

Blue Origin Multiple locations

FPGA Design for Test

1mo

Front-End Integration Engineer

NVIDIA Bengaluru, Karnataka

ASIC RTL

1mo

Formal Verification Engineer

NVIDIA Shanghai, Shanghai

ASIC RTL

1mo

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1mo

Senior Digital Design Engineer

NXP Semiconductors Pune, Maharashtra

Verilog System Verilog

1mo

Senior Physical Design Engineer

NXP Semiconductors Pune, Maharashtra

RTL STA

1mo

ASIC Physical Verification Lead

NXP Semiconductors Pune, Maharashtra

ASIC RTL

1mo

Sr. Principal Technical Program Manager – Digital IP Development

NXP Semiconductors Austin, Texas

RTL Synthesis

1mo

Senior Verification Engineer

NXP Semiconductors Austin, Texas

VHDL Verilog

1mo

Senior Engineer II - IP Verification

Microchip Technology Hyderabad, Telangana

FPGA UVM

1mo

Software Engineer

Microchip Technology Toronto, Ontario

FPGA Digital Design

1mo

FPGA Design Lead

BAE Systems Multiple locations

VHDL Verilog

1mo

ASIC Technical Project Manager

Hudson River Trading New York, NY, United States

ASIC RTL

1mo

Aug. 27, 2026

Sr CAD Engineer (Digital)

Analog Devices Bangalore, India

RTL Synthesis

1mo

Senior ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

Verilog ASIC

1mo

ASIC Design Engineer 2

HPE Juniper Networks Sunnyvale, California

Verilog System Verilog

1mo

Principal Electrical Engineer

BAE Systems Dallas, Texas

VHDL Verilog

1mo

Formal Verification Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

Senior DFT Methodology - Data Analytics and Applied AI Engineer

NVIDIA Santa Clara, California

DFT Design for Test

1mo

SLD Avionics FPGA Engineer III - Lunar Permanence

Blue Origin Denver, Colorado

VHDL Verilog

1mo

Senior Test Integration Engineer – HLS Test Definition

Blue Origin Space Coast, Florida

HLS Verification

1mo

Systems Engineer II — Lunar Human Landing System (HLS)

Blue Origin Multiple locations

HLS Verification

1mo

Shift Leader - Cleaning, Passivation, and Verification Lab

Blue Origin Greater Seattle Area

Verification

1mo

CPU Microarchitect/RTL Engineer

Apple Austin, Texas

VHDL Verilog

1mo

Senior Engineer I - ASIC Verification

Microchip Technology Penang, Malaysia

SystemVerilog RTL

1mo

Principal Engineer - CAD (Physical Verification)

Microchip Technology Chandler, Arizona

Verification

1mo

Technical Staff Engineer - Verification

Microchip Technology Multiple locations

Verilog System Verilog

1mo