Aug. 27, 2026

FPGA Designer

Fidus Systems Austin, Texas

Remote VHDL Verilog

1mo

Lead Hardware Engineer

A2e Technologies San Diego, California

VHDL Verilog

1mo

Staff Engineer, Diagnostic Development

Tenstorrent Toronto, Ontario

ASIC SOC

1mo

Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Tenstorrent Multiple locations

SystemVerilog UVM

1mo

Aug. 26, 2026

ASIC Engineering Intern, Networking Chip Design - 2027

NVIDIA Shanghai, Shanghai

RTL Verification

1mo

Senior Formal Verification Engineer

NVIDIA Bengaluru, Karnataka

RTL Verification

1mo

Senior Formal Verification Engineer

NVIDIA Yokneam, Israel

Verification

1mo

ASIC Physical Design Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC RTL

1mo

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

1mo

ASIC Design Engineer

HPE Juniper Networks Bengaluru, Karnataka

FPGA ASIC

1mo

Silicon Validation/Emulation Design Engineer

Apple Sunnyvale, United States

RTL SOC

1mo

Associate Design Verification Engineer

Analog Devices Dallas, Texas

Verilog SystemVerilog

1mo

Staff Digital Design Engineer

Analog Devices Bari, Apulia

Verilog System Verilog

1mo

Principal FPGA Digital Design Engineer - Signing Bonus

BAE Systems Nashua, New Hampshire

VHDL Verilog

1mo

Sr. Staff Engineer - Digital Design Verification

Ambiq Micro, Inc. Austin, Texas

Verilog SystemVerilog

1mo

Senior Systems Verification & Certification Engineer

ALTEN Technology USA Burlington, Vermont

Verification

1mo

Aug. 25, 2026

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

1mo

Senior SRAM Engineer

NVIDIA Santa Clara, California

Verilog Static Timing

1mo

ASIC Physical Design Engineer (RDSS Intern)

NVIDIA Hsinchu, Hsinchu

ASIC RTL

1mo

ASIC Physical Design Intern - 2027

NVIDIA Hsinchu, Hsinchu

ASIC RTL

1mo

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

1mo

Design Engineer - STA

Broadcom Fort Collins, Colorado

ASIC STA

1mo

SENIOR DESIGN ENGR

NXP Semiconductors Multiple locations

Verilog SystemVerilog

1mo

Principal CAD Engineer Digital Verification

NXP Semiconductors Noida, Uttar Pradesh

Verilog System Verilog

1mo

Principal ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

Technical Staff Engineer - Design

Microchip Technology Bangalore, India

Verilog System Verilog

1mo

Principal Electrical Engineer

BAE Systems Hudson, New Hampshire

VHDL Verilog

1mo

Systems Architecture, Integration, and Test Engineer (Test & Verification)

Saronic Austin, Texas

Verification

1mo

Senior Electrical Engineer – PCBA Schematic & Layout

Saronic Austin, Texas

FPGA DFT

1mo

Senior Staff Digital Design Engineer - Audio DSP Algorithm

Syntiant Bengaluru, Karnataka

Verilog System Verilog

1mo

AMS Verification Engineer (RFIC Engineering)

SpaceX Redmond, Washington

Verilog System Verilog

1mo

AMS Verification Engineer (RFIC Engineering)

SpaceX Irvine, California

Verilog System Verilog

1mo

Manufacturing Engineer - Data Center Hardware

Anthropic Remote-Friendly, United States

DFT Design for Test

1mo

Aug. 24, 2026

Senior Firmware PHY Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

Verification

1mo

Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Logic Design

1mo

Aug. 23, 2026

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Ottawa, Ontario

Verilog SystemVerilog

1mo

ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal

Celero Communications, Inc. Irvine, California

Verilog SystemVerilog

1mo

Aug. 22, 2026

Senior Engineer I - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

1mo

Principal Engineer -Software Design

Microchip Technology Hyderabad, Telangana

FPGA Synthesis

1mo

Avionics Engineer II - Inverter Development

Blue Origin Greater Seattle Area

FPGA Design for Test

1mo

Associate Digital Design Engineer

Analog Devices Durham, North Carolina

Verilog SystemVerilog

1mo

Principal / Senior Principal Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman Baltimore, Maryland

VHDL Verilog

1mo

Staff Radar Modeling Simulation Analysis Systems Engineer

Northrop Grumman Baltimore, Maryland

VHDL Verilog

1mo

Senior Principal Digital Engineer

Northrop Grumman Woodland Hills, California

VHDL Verilog

1mo

CPU Physical Design Engineer

Intel Bangalore, India

VHDL Verilog

1mo

CPU Floorplan Lead

Intel Bangalore, India

ASIC Logic Design

1mo

NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China

NVIDIA Shanghai, Shanghai

ASIC RTL

1mo

NVIDIA 2027 New College Graduate: GPU Architecture Engineering - China

NVIDIA Multiple locations

ASIC RTL

1mo

ASIC Methodology, Flow and Integration Engineer

NVIDIA Multiple locations

ASIC RTL

1mo

Physical Design Power Optimization and Modeling Engineer

NVIDIA Tel Aviv, Tel Aviv District

STA Place and Route

1mo