Sept. 14, 2026

Staff Design Verification Engineer – CPU Core Formal Verification

SiFive Multiple locations

ASIC RTL

18d

Staff Design Verification Engineer – CPU Core Formal Verification

SiFive Austin, Texas

ASIC RTL

18d

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

18d

Senior Design Verification Engineer – CPU Core Verification (Vector)

SiFive Multiple locations

SystemVerilog RTL

18d

Product Power Engineer

SiFive Multiple locations

FPGA ASIC

18d

Sept. 13, 2026

Low Power Design Engineer(NPU)-Sr Lead

Qualcomm Bangalore, India

RTL Synthesis

19d

Sept. 12, 2026

GPU Validation and Emulation Engineer, Senior

Qualcomm San Diego, California

Verilog System Verilog

20d

Modem design/RTL (Sr Staff)

Qualcomm Bangalore, India

VHDL Verilog

20d

(Structural ATPG) APAC Digital SOC Test Engineer

Qualcomm Hsinchu City, Taiwan

DFT Design for Test

20d

EDA/CAD SW Engineer (Multiple Levels)

Qualcomm San Diego, California

Verilog System Verilog

20d

FY27 Intern - Display IP Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

20d

FY27 Intern - Compute DSP/AI Processor Engineering Internship - Canada (16 months)

Qualcomm Markham, Ontario

VHDL Verilog

20d

Analog Engineer, Principal

Qualcomm Toronto, Ontario

VHDL Verilog

20d

FPGA Firmware Engineer / FPGA Design Engineer

Qualcomm San Diego, California

Verilog System Verilog

20d

Staff / Senior Staff Microarchitect / System Engineer

Qualcomm Noida, Uttar Pradesh

Verilog UVM

20d

Staff design Verification Engineer

Qualcomm Noida, Uttar Pradesh

Verilog System Verilog

20d

Staff SOC Verification Engineer

Qualcomm Noida, Uttar Pradesh

Verilog System Verilog

20d

Performance Optimization Architect/Manager

Qualcomm Bangalore, India

Verilog System Verilog

20d

Senior Lead Pre/Post Silicon Validation Engineer - SoC Security and access control Expertise

Qualcomm Bangalore, India

FPGA ASIC

20d

Senior SoC Physical Design Engineer

Qualcomm Bangalore, India

FPGA ASIC

20d

VLSI Software Engineer

Qualcomm Tijuana, Baja California

ASIC RTL

20d

Test Engineer Intern - Summer 2027

NXP Semiconductors Austin, Texas

Digital Design SOC

20d

ASIC Design Automation Engineer

Broadcom Fort Collins, Colorado

Verilog ASIC

20d

DSP System Architect

Broadcom Irvine, California

ASIC RTL

20d

Senior DFT Engineer

NVIDIA Multiple locations

RTL DFT

20d

Power Architecture Engineer

NVIDIA Bengaluru, Karnataka

Verilog ASIC

20d

Senior Hardware Security Architect

NVIDIA Santa Clara, California

Verilog ASIC

20d

Silicon Co-design Intern - 2027

NVIDIA Shanghai, Shanghai

ASIC Digital Design

20d

Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave

Blue Origin San Diego, California

Verilog SystemVerilog

20d

Senior Electrical Engineer – TeraWave High-Speed Digital & Networking Payload Hardware

Blue Origin Greater Seattle Area

FPGA DFT

20d

Aerospace Systems Engineer III - Blue Ring Space Vehicle Requirements & Verification Architect

Blue Origin Multiple locations

Verification

20d

Sr. Manufacturing PCBA Design & SMT Fab DFX Engineer

Blue Origin Cupertino, California

FPGA ASIC

20d

Senior Electrical Engineer - Power Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

20d

Senior Electrical Engineer - Circuit Design - TeraWave

Blue Origin Denver, Colorado

FPGA Digital Design

20d

RFIC Layout Engineer

Apple Multiple Locations

RTL SOC

20d

GPU IP Verification Engineer

Intel Bangalore, India

VHDL Verilog

20d

GPU IP Integration Model Build Engineer

Intel Bangalore, India

UVM OVM

20d

Senior PDK Support Engineer (Physical Verification)

Intel Multiple locations

SOC Verification

20d

CPU Circuit Design Engineer

Intel Bangalore, India

Verilog Digital Design

20d

Senior Engineer II - Validation (ASIC)

Microchip Technology Basking Ridge, New Jersey

ASIC

20d

Senior Principal FPGA Verification Engineer - $30K Sign-On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

20d

Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Multiple locations

Verilog SystemVerilog

20d

Summer Program Intern

Marvell Córdoba, Córdoba

Verilog Digital Design

20d

Electrical Engineer

CACI Florham Park, NJ, US

VHDL Verilog

20d

Electrical Engineer

CACI Florham Park, NJ, US

VHDL Verilog

20d

Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

20d

Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

20d

Physical Design Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

20d

Design Verification Engineer - Compute

MatX Mountain View, California

Remote SystemVerilog UVM

20d

Sept. 11, 2026

Principal FPGA Designer – TeraWave

Blue Origin Greater Seattle Area

VHDL Verilog

21d