Sept. 15, 2026

Principal / Sr. Principal PCB Layout Design Engineer

Northrop Grumman Woodland Hills, California

DFT Design for Test

17d

RTL Design Engineer

Intel Multiple locations

VHDL Verilog

17d

Senior DFT Logic Design Engineer

Intel Multiple locations

ASIC RTL

17d

Digital Verification Engineer - MCU

NXP Semiconductors Catania, Sicily

SystemVerilog UVM

17d

Mixed Signal Design Engineer

NXP Semiconductors Tianjin, Tianjin

SOC IP Design

17d

Architect - GPU Performance

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

17d

Senior Architect, GPU and SoC Modeling

NVIDIA Santa Clara, California

SOC

17d

Senior ASIC Design Engineer

NVIDIA Santa Clara, California

Verilog System Verilog

17d

Manager, Project Management - Chip Design

NVIDIA Tel Aviv, Tel Aviv District

Verilog SystemVerilog

17d

NVTHERM SoC Verification Intern, Tegra - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

17d

Design Engineer

Silicon Labs Oslo

Digital Design Synthesis

17d

Principal Field Application Engineer

SiFive Shanghai, Shanghai

FPGA RTL

17d

Senior ASIC Diagnostic Engineer

HPE Juniper Networks Bloomington, Minnesota

ASIC

17d

Senior Principal ASIC Design Engineer

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

17d

SoC Audio Architect, Platform Architecture

Apple Multiple Locations

SOC IP Design

17d

SoC Audio Engineer, Platform Architecture

Apple Multiple Locations

SOC IP Design

17d

Infra Systems Physical Architect

Qualcomm San Diego, California

ASIC Place and Route

17d

DRAM PHY Designer, up to Staff

Qualcomm Hsinchu City, Taiwan

ASIC RTL

17d

SMMU Senior Lead Design Verification Engineer

Qualcomm Bangalore, India

Verilog System Verilog

17d

RTL Design (Director)

Qualcomm Hyderabad, Telangana

Digital Design Synthesis

17d

Design Verification Engineer, Senior Staff

Qualcomm Toronto, Ontario

SystemVerilog ASIC

17d

SoC Design Verification Engineer (Up to Principal Level)

Qualcomm Ho Chi Minh City, Hồ Chí Minh

SystemVerilog FPGA

17d

SoC RTL Design Engineer (Up to Principal Level)

Qualcomm Ho Chi Minh City, Hồ Chí Minh

Verilog SystemVerilog

17d

CPU Physical Design Engineer

Qualcomm Austin, Texas

VHDL Verilog

17d

SOC Power Architect

Qualcomm San Diego, California

ASIC SOC

17d

Camera VI Engineer

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

17d

Senior Principal FPGA Design Engineer

BAE Systems Totowa, New Jersey

VHDL Verilog

17d

Test and Verification Engineer

Philips Shenzhen

Verification

17d

DFT Manager

Broadcom IND-Bangalore Electronic City - S1

ASIC DFT

17d

Digital Design Verification Engineer

Broadcom Multiple locations

UVM SOC

17d

Senior Embedded Engineer, EW

Anduril Costa Mesa, California

VHDL Verilog

17d

Electrical Manufacturing Engineer

Anduril Atlanta, Georgia

FPGA Digital Design

17d

Electro-Optic Systems Architect

Lightmatter Multiple locations

RTL Digital Design

17d

Senior FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

17d

Sept. 14, 2026

Embedded Firmware Design Engineer (m/f/d)

NXP Semiconductors Gratkorn

Digital Design HDL

18d

GSoC Design Verification Engineer

Qualcomm San Diego, California

Verilog System Verilog

18d

GPU Design Implementation Engineer

Qualcomm San Diego, California

ASIC RTL

18d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

18d

SoC Power Design Engineer (Engineer - Staff Eng)

Qualcomm San Diego, California

VHDL Verilog

18d

Power Modelling Engineer, Staff

Qualcomm Bangalore, India

ASIC RTL

18d

Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Qualcomm San Diego, California

ASIC RTL

18d

SoC Performance Architect (Server CPU) - PhD New Grads Welcome!

Qualcomm Multiple locations

SOC

18d

Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

Qualcomm Guyancourt, Île-de-France

ASIC RTL

18d

Physical Design Engineer

Qualcomm San Diego, California

ASIC RTL

18d

Staff Design Verification Engineer – Coherent Interconnect (CHI)

SiFive Multiple locations

SystemVerilog ASIC

18d

System Validation Engineer (New Grads)

SiFive Multiple locations

Verilog FPGA

18d

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

18d

Staff Design Verification Engineer – CPU Core Verification (Vector)

SiFive Multiple locations

SystemVerilog ASIC

18d

Staff Design Verification Engineer – CPU Core Verification (ALU)

SiFive Multiple locations

SystemVerilog ASIC

18d

Staff Design Verification Engineer – CPU Core Formal Verification

SiFive Multiple locations

ASIC RTL

18d