Sept. 22, 2026

Senior Mixed Signal Verification Engineer

NXP Semiconductors Catania, Sicily

SystemVerilog Digital Design

10d

ASIC Package Design Project Manager

Broadcom Fort Collins, Colorado

ASIC

10d

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

10d

IC Verification Engineer

Broadcom San Jose, California

Verilog System Verilog

10d

Staff Engineer

Broadcom IND-Bangalore Electronic City - S1

Verilog RTL

10d

SoC Power and Performance Engineer

Intel Santa Clara, California

SOC

10d

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

10d

ASIC Principal Engineer

HPE Juniper Networks Bengaluru, Karnataka

Verilog ASIC

10d

VLSI Engineer II Graduate

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

10d

Systems / Software Engineer I Graduate

HPE Juniper Networks Roseville, California

FPGA Logic Design

10d

VLSI Engineer I Graduate

HPE Juniper Networks Sunnyvale, California

FPGA Logic Design

10d

Digital IC Design Intern, BS - Summer 2027

Marvell Multiple locations

Verilog ASIC

10d

Digital IC Design Intern, MS - Summer 2027

Marvell Multiple locations

Verilog ASIC

10d

HLS Software Systems Engineer ll - Lunar Permanence

Blue Origin Denver, Colorado

Verification

10d

HLS Autonomy Software Systems Engineer III

Blue Origin Denver, Colorado

HLS Verification

10d

Sr HLS Software Verification Engineer – Lunar Permanence

Blue Origin Denver, Colorado

Verification

10d

ASIC Verification Engineer - Clocks

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

10d

Senior GPU Memory Architect

NVIDIA Multiple locations

VHDL Verilog

10d

Associate Staff Design Modeling Engineer

Silicon Labs Austin, Texas

RTL UVM

10d

Sr. Manager, Design Verification

Analog Devices Hyderabad, Telangana

SystemVerilog FPGA

10d

Senior Design Verification Engineer

Analog Devices Hyderabad, Telangana

SystemVerilog FPGA

10d

Senior Design Verification Engineer

Analog Devices Hyderabad, Telangana

SystemVerilog FPGA

10d

Senior Design Verification Engineer

Analog Devices Hyderabad, Telangana

SystemVerilog FPGA

10d

Design Verification Engineer

Analog Devices Hyderabad, Telangana

Verilog SystemVerilog

10d

Design Verification Engineer

Analog Devices Hyderabad, Telangana

Verilog SystemVerilog

10d

Embedded Systems Applications Engineer

Analog Devices Wilmington, Massachusetts

VHDL Verilog

10d

Technical Project Manager

Fidus Systems Ottawa, Ontario

FPGA ASIC

10d

Technical Project Manager

Fidus Systems Seattle, Washington

Remote FPGA ASIC

10d

Principal Physical Verification Engineer

Celero Communications, Inc. San Jose, California

Verification

10d

Principal Physical Verification Engineer

Celero Communications, Inc. Irvine, California

Verification

10d

Principal Physical Design Engineer

Celero Communications, Inc. San Jose, California

ASIC RTL

10d

Principal Physical Design Engineer

Celero Communications, Inc. Irvine, California

ASIC RTL

10d

Director of Embedded Software & FPGA Engineering

Loft Orbital Golden, Colorado

FPGA Verification

10d

Sept. 21, 2026

Senior ASIC Design Verification Engineer - Slingshot

HPE Juniper Networks Bloomington, Minnesota

SystemVerilog FPGA

11d

ASIC Verification Engineer

HPE Juniper Networks Durham, North Carolina

SystemVerilog ASIC

11d

Senior Digital Design Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog SystemVerilog

11d

Principal SoC Program Manager - MCU

NXP Semiconductors Catania, Sicily

SOC

11d

FPGA and Emulation Prototyping Engineer - MCU

NXP Semiconductors Catania, Sicily

Verilog System Verilog

11d

Senior Chip Design Verification Engineer

NVIDIA Tel Aviv, Tel Aviv District

RTL Verification

11d

Mixed Signal Design Verification Engineer

Allegro MicroSystems Manchester, New Hampshire

Verilog SystemVerilog

11d

Mixed Signal Design Verification Engineer

Allegro MicroSystems Prague, Praha, Hlavní město

Verilog SystemVerilog

11d

Mixed Signal Design Verification Engineer

Allegro MicroSystems Buenos Aires, Buenos Aires

Verification

11d

Analog / Mixed-Signal Sensor IP Design Engineer - Cork, Ireland

Qualcomm Cork, Munster

Verilog ASIC

11d

Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland

Qualcomm Cork, Munster

Verilog ASIC

11d

Senior Test and Verification Engineer

Philips Shenzhen

Verification

11d

Sept. 20, 2026

DSP Systems Engineer, Staff

Qualcomm Toronto, Ontario

RTL Digital Design

12d

Cross-Functional Engineer, Staff

Qualcomm Multiple locations

VHDL Verilog

12d

Sept. 19, 2026

Digital Hardware Engineer

BAE Systems Nashua, New Hampshire

FPGA Digital Design

13d

Senior Engineer - CPU Verification (RISCV Vector,ALU, FPU Verification)

SiFive Bengaluru, Karnataka

SystemVerilog ASIC

13d

Director, Digital Design

Analog Devices Bangalore, India

FPGA ASIC

13d