UVM Jobs

Browse open UVM positions for FPGA, ASIC, and RTL engineers.

All Locations California 151 Bangalore 73 Texas 70 Austin, TX 67 Santa Clara, CA 55 Telangana 44 Hyderabad 44 Karnataka 37

Senior Staff Verification Engineer

Axiado Hyderabad, Telangana

SystemVerilog FPGA

1mo

Principal Senior Engineer - FPGA Design - $20K Sign On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

1mo

Senior Principal II Engineer – FPGA Design - $40K Sign On Bonus

BAE Systems Chantilly, Virginia

VHDL Verilog

1mo

Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)

BAE Systems Multiple locations

VHDL SystemVerilog

1mo

Senior Principal FPGA Verification Engineer - $15K Sign-On Bonus

BAE Systems Westminster, Colorado

VHDL Verilog

1mo

Engineer Senior - FPGA Verification

BAE Systems Westminster, Colorado

VHDL Verilog

1mo

Engineer II - FPGA Verification

BAE Systems Westminster, Colorado

Verilog System Verilog

1mo

Senior FPGA Verification Engineer - $30K Sign On Bonus

BAE Systems Westminster, Colorado

Verilog System Verilog

1mo

Principal FPGA Digital Design Engineer - Sign-on Bonus

BAE Systems Nashua, New Hampshire

VHDL Verilog

1mo

Digital Verification Engineer

Neuralink South San Francisco, California, United States

SystemVerilog FPGA

2mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

2mo

Staff Design Verification Engineer – Cache Verification

SiFive Hsinchu, Hsinchu

SystemVerilog FPGA

2mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

2mo

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

2mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

2mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

2mo

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

2mo

Senior Staff RTL Design Engineer - CPU Frontend

SiFive Santa Clara, California

VHDL Verilog

2mo

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

2mo

Mixed-Signal Verification Engineer

Apple Multiple Locations

Verilog System Verilog

2mo

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