UVM Jobs

Design Verification - Intern

Marvell Petah-Tikva

Verilog System Verilog

18h

ASICS Design Verification Engineer - Multiple levels

Qualcomm Vancouver, British Columbia

VHDL Verilog

18h

AICS Design Verification Engineer- Multiple levels

Qualcomm Vancouver, British Columbia

VHDL Verilog

18h

NOC DV Engineer

Qualcomm Bangalore, India

SystemVerilog FPGA

18h

Staff FPGA Digital Engineer - 5

Northrop Grumman Chandler, Arizona

VHDL Verilog

19h

STAFF ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

20h

ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

20h

Design Verification Engineer

Micron Jalisco, Chiapas

Verilog SystemVerilog

20h

ENGINEER - HBM VERIFICATION

Micron Jalisco, Chiapas

UVM DFT

20h

Engineering Manager III – Tactical Electronics FPGA Development

BAE Systems Westminster, Colorado

VHDL Verilog

1d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1d

Design Verification Engineer II

Silicon Labs Singapore, Central Singapore

SystemVerilog RTL

1d

Senior FPGA Developer

Philips Suzhou

VHDL Verilog

1d

Design Verification Engineer

Micron Jalisco, Chiapas

Verilog SystemVerilog

1d

New College Grad - HBM SoC Design Engineer/Architect

Micron Multiple locations

VHDL Verilog

1d

Design Verification Intern

Ambiq Micro, Inc. Singapore, Central Singapore

Verilog SystemVerilog

1d

IP Design Verification Engineer

Intel Multiple locations

Verilog SystemVerilog

2d

Senior Engineer - Design Verification

SiFive Ahmedabad, Gujarat

SystemVerilog FPGA

2d

Senior Verification Engineer, PCIE

NVIDIA Bengaluru, Karnataka

Verilog SystemVerilog

2d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

2d