UVM Jobs in Santa Clara, CA

ASIC Design Verification Engineer (Security Group) - Sr Staff

Qualcomm Santa Clara, California

SystemVerilog FPGA

3h

IP Design Verification Engineer

Intel Santa Clara, California

VHDL Verilog

1d

Design Verification Engineer

Intel Multiple locations

SystemVerilog FPGA

1d

IP Design Verification Engineer

Intel Santa Clara, California

Verilog SystemVerilog

1d

Senior Verification Engineer – High Speed Coherent Interconnect Hub

NVIDIA Santa Clara, California

SystemVerilog FPGA

3d

SoC Design Verification Engineer

Intel Santa Clara, California

RTL UVM

3d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

7d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

7d

ASIC Verification Engineer - GPU

NVIDIA Multiple locations

Verilog System Verilog

8d

Low Power ASIC Engineer - New College Grad 2027

NVIDIA Santa Clara, California

Verilog SystemVerilog

10d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Santa Clara, California

VHDL Verilog

10d

Pre-Silicon Verification Engineer

Intel Multiple locations

Verilog System Verilog

14d

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA Santa Clara, California

SystemVerilog ASIC

14d

Senior Full-Chip RTL Integration Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

16d

PCIe Design Verification Intern - Spring 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

17d

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

21d

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

24d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

25d

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Santa Clara, California

SystemVerilog FPGA

25d

Senior ASIC Verification Engineer - GPU

NVIDIA Santa Clara, California

Verilog System Verilog

1mo