UVM Jobs in Santa Clara, CA

GPU Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

2d

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Santa Clara, California

SystemVerilog FPGA

2d

SoC Verification Engineer

Intel Multiple locations

RTL UVM

6d

Senior ASIC Verification Engineer - GPU

NVIDIA Santa Clara, California

Verilog System Verilog

7d

Senior ASIC Design Verification Engineer - LPU

NVIDIA Multiple locations

SystemVerilog ASIC

8d

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

14d

Midcore Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

14d

Front End Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

15d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

17d

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

17d

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

17d

Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

20d

Sr. Staff Engineer, SoC Design Verification

Tenstorrent Multiple locations

UVM SOC

21d

Senior Firmware Verification and Bringup Engineer

NVIDIA Santa Clara, California

SystemVerilog RTL

22d

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

26d

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

26d

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

26d

Sr. Staff Engineer, CPU (Front-End) Verification

Tenstorrent Multiple locations

SystemVerilog RTL

26d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

27d