UVM Jobs

Staff Design Verification Engineer

Cerebras Systems Sunnyvale, California

SystemVerilog RTL

1mo

Design Verification Manager

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

Senior Design Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog FPGA

1mo

Senior ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

ASIC Verification Engineer

HPE Juniper Networks Sunnyvale, California

SystemVerilog ASIC

1mo

Manager, DFT - Post Silicon

NVIDIA Tel Aviv, Tel Aviv District

Verilog RTL

1mo

Mixed Signal Design Verification (MSDV) Engineer

Nexperia Dallas, Texas

Verilog SystemVerilog

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

Senior USB IP Design Verification Engineer

Intel Multiple locations

Verilog System Verilog

1mo

Senior Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

1mo

CPU Verification Engineer

Intel Austin, Texas

SystemVerilog RTL

1mo

IP RTL Senior Design Engineer

Intel Bangalore, India

Verilog System Verilog

1mo

Senior Engineer II - Verification

Microchip Technology Dresden, Saxony

Verilog System Verilog

1mo

Senior Technical Staff Engineer - Verification

Microchip Technology Chandler, Arizona

Verilog SystemVerilog

1mo

Sr. Engineer II – Verification

Microchip Technology Bangalore, India

VHDL Verilog

1mo

Director, Design Engineering – Data Center Solutions (DCS)

Microchip Technology Bangalore, India

Verilog SystemVerilog

1mo

Principal Engineer - Verification

Microchip Technology Chennai, Tamil Nadu

Verilog System Verilog

1mo

Principal Digital Verification Engineer

Microchip Technology Bangalore, India

Verilog System Verilog

1mo

Senior Technical Staff Engineer – Emulation

Microchip Technology Multiple locations

Verilog System Verilog

1mo

Technical Staff Engineer - Verification

Microchip Technology Multiple locations

Verilog System Verilog

1mo