UVM Jobs

Browse open UVM positions for FPGA, ASIC, and RTL engineers.

All Locations California 151 Bangalore 73 Texas 70 Austin, TX 67 Santa Clara, CA 55 Telangana 44 Hyderabad 44 Karnataka 37

Principal Engineer, Design Verification Engineering

Analog Devices Dublin, Leinster

Verilog SystemVerilog

1mo

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

1mo

Principal AI Accelerator Architect Lead

Analog Devices Multiple locations

SystemVerilog ASIC

1mo

Staff Design Verification Engineer

Analog Devices Edinburgh, South Carolina

Verilog FPGA

1mo

Senior Engineer, Digital Design Engineering

Analog Devices Multiple locations

Verilog SystemVerilog

1mo

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

SystemVerilog RTL

1mo

Staff Design Verification Engineer

Analog Devices Bangalore, India

Verilog SystemVerilog

1mo

Senior Verification Engineer

Analog Devices Wilmington, Massachusetts

Verilog SystemVerilog

1mo

Principal Engineer, Design Verification

Analog Devices Multiple locations

Verilog SystemVerilog

1mo

Mixed Signal Design Verification Engineer

Analog Devices Wilmington, Massachusetts

SystemVerilog RTL

1mo

Staff Digital Verification Engineer

Analog Devices Singapore, Central Singapore

SystemVerilog RTL

1mo

Digital Verification Lead

Analog Devices Singapore, Central Singapore

SystemVerilog UVM

1mo

Staff Design Verification Engineer – SoC and eFPGA

Analog Devices San Jose, California

Verilog SystemVerilog

1mo

SoC Verification Engineer

Intel Bangalore, India

RTL UVM

1mo

Senior CPU Design Verification Engineer

Intel Multiple locations

SystemVerilog RTL

1mo

Sr. Staff Design Verification Engineer

d-Matrix Multiple locations

Remote SystemVerilog ASIC

1mo

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Principal Mixed Signal Design Verification, Team Lead

Allegro MicroSystems Musselburgh, Scotland

SystemVerilog UVM

1mo

Principal Digital Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

Principal Analog Mixed Signal Verification Engineer

NXP Semiconductors Chandler (Office)

Verilog SystemVerilog

1mo

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