UVM Jobs

SOC Design Verification Engineer– Pre-Si/Post-Si Verification

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

28d

SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification

Qualcomm Tijuana, Baja California

Verilog SystemVerilog

28d

Staff ASIC Verification Engineer, Low Power AI

Qualcomm Markham, Ontario

VHDL Verilog

28d

Security HW Design Verification Engineer, Senior - Cork, Ireland

Qualcomm Cork, Munster

ASIC UVM

28d

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

SystemVerilog RTL

29d

Staff Engineer, Design Verification Engineering

Analog Devices Bangalore, India

Verilog SystemVerilog

29d

Modem Hardware Design Verification Engineer – AI Driven Next Gen Modem Hardware Development, Staff

Qualcomm Boxborough, Massachusetts

VHDL Verilog

29d

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

29d

Design Verification Intern, BS - Summer 2027

Marvell Multiple locations

VHDL ASIC

29d

Design Verification Intern, MS - Summer 2027

Marvell Multiple locations

VHDL ASIC

29d

ASIC Design and Verification Intern, SOC - 2027

NVIDIA Shanghai, Shanghai

Verilog SystemVerilog

29d

Sr Design Verification Eng

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

29d

Sr. Staff Engineer, CPU (Front-End) Verification

Tenstorrent Multiple locations

SystemVerilog RTL

29d

ASIC Verification Engineer - Clocks

NVIDIA Bengaluru, Karnataka

Verilog System Verilog

1mo

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

1mo

ASIC Design Verification Engineer, up to Sr. Staff

Qualcomm Hsinchu City, Taiwan

Verilog System Verilog

1mo

Staff Engineer CPU DV

SiFive Hyderabad, Telangana

Verilog System Verilog

1mo

Staff Design Verification

SiFive Hyderabad, Telangana

SystemVerilog ASIC

1mo

Senior Design Verification Engineer

SiFive Hyderabad, Telangana

Verilog SystemVerilog

1mo

Senior Design Verification Engineer - FPGA

BAE Systems Multiple locations

VHDL SystemVerilog

1mo