UVM Jobs

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

3mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

ASIC RTL

3mo

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

ASIC RTL

3mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

FPGA ASIC

3mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

FPGA ASIC

3mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

FPGA ASIC

3mo

Principal Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

FPGA ASIC

3mo

Design Verification Engineer (Silicon Engineering)

SpaceX Redmond, Washington

SystemVerilog ASIC

3mo

Design Verification Engineer (Silicon Engineering)

SpaceX Irvine, California

SystemVerilog ASIC

3mo

Design Verification Engineer (Silicon Engineering)

SpaceX Palo Alto, California

SystemVerilog ASIC

3mo

Design Verification Engineer (Silicon Engineering)

SpaceX Austin, Texas

SystemVerilog ASIC

3mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

3mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

3mo

Staff Engineer, CPU Core Verification

Tenstorrent Bengaluru, Karnataka

RTL UVM

3mo

Sr Staff Engineer, SoC RTL Design

Tenstorrent Toronto, Ontario

VHDL Verilog

3mo

Sr/Staff Engineer, Design Verification,System IP

Tenstorrent Bengaluru, Karnataka

SystemVerilog ASIC

3mo

Design Verification Lead, AI Hardware

Tenstorrent Toronto, Ontario

SystemVerilog FPGA

3mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

3mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

3mo

Manager/Director of Hardware Engineering

Baya Systems Santa Clara, California

Verilog SystemVerilog

3mo