STA Jobs in California

Physical Design (Multiple levels)

Qualcomm San Diego, California

ASIC RTL

1mo

ASIC Methodology Engineer

Qualcomm Santa Clara, California

ASIC RTL

1mo

CPU STA CAD Engineer

Qualcomm Multiple locations

STA Static Timing

1mo

Implementation Timing / STA Design Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

ASIC DFT Engineer

Broadcom San Jose, California

Verilog ASIC

1mo

Digital Design Engineer Intern

Analog Devices Multiple locations

VHDL Verilog

2mo

Senior SRAM Engineer

NVIDIA Santa Clara, California

Verilog Static Timing

2mo

Senior STA Signoff Methodology Engineer

NVIDIA Multiple locations

ASIC STA

2mo

Senior SoC Power Analysis & Optimization Engineer

MatX Multiple locations

Remote Verilog SystemVerilog

2mo

NVIDIA 2027 Internships: Hardware Physical Design / VLSI

NVIDIA Santa Clara, California

Logic Design Digital Design

2mo

NVIDIA 2027 Internships: Hardware Design for Test (DFT)

NVIDIA Santa Clara, California

Digital Design STA

2mo

NVIDIA 2027 Internships: Hardware ASIC Design

NVIDIA Santa Clara, California

VHDL Verilog

2mo

Director AI/ML Driven ASIC Design and Implementation Automation

NXP Semiconductors Multiple locations

VHDL Verilog

2mo

Associate Digital Design Engineer

Analog Devices San Jose, California

Verilog SystemVerilog

2mo

Senior Physical Design Engineer

Samsung Semiconductor San Jose, California

ASIC RTL

2mo

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

2mo

Senior Principal Digital IC Design Engineer

Marvell Santa Clara, California

Verilog SystemVerilog

2mo

Principal, IC Digital Design Engineer

Marvell Irvine, California

SystemVerilog FPGA

2mo

Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Marvell Santa Clara, California

ASIC RTL

2mo

Lead ASIC Design Engineer

Broadcom San Jose, California

Verilog SystemVerilog

2mo