STA Jobs in California

Sr. Staff / Principal Physical Design Engineer

SK hynix memory solutions America Inc. San Jose, California

ASIC RTL

27d

Senior Staff Engineer, Multi-die 3DIC

Marvell Santa Clara, California

ASIC RTL

1mo

Physical Design Engineer, Timing

Tenstorrent Multiple locations

STA Static Timing

1mo

Digital IC Design Intern, BS - Summer 2027

Marvell Multiple locations

Verilog ASIC

1mo

Digital IC Design Intern, MS - Summer 2027

Marvell Multiple locations

Verilog ASIC

1mo

Principal Physical Design Engineer

Celero Communications, Inc. San Jose, California

ASIC RTL

1mo

Principal Physical Design Engineer

Celero Communications, Inc. Irvine, California

ASIC RTL

1mo

RF/Analog Design/Mixed-Signal Engineering Internship – Summer 2027

Qualcomm Multiple locations

Verilog SystemVerilog

1mo

Senior Staff Digital Design Engineer

Marvell Multiple locations

SystemVerilog FPGA

1mo

Analog Mixed-Signal IC Design Engineer (Custom Digital Timing Characterization and Liberty Modeling) – TeraWave

Blue Origin San Diego, California

Verilog SystemVerilog

1mo

Physical Design Engineer (Silicon Engineering)

SpaceX Palo Alto, California

ASIC RTL

1mo

Physical Design Engineer (Silicon Engineering)

SpaceX Irvine, California

ASIC RTL

1mo

Physical Design CPU Methodology Engineer

Tenstorrent Santa Clara, California

ASIC RTL

1mo

CPU Sever FV/CLP/STA engineer

Qualcomm Santa Clara, California

FPGA STA

1mo

ASIC/RTL Design Engineer for High-speed Interfaces

Qualcomm San Diego, California

ASIC RTL

1mo

CPU SRAM Design & Layout Engineer

Qualcomm Santa Clara, California

Verilog Static Timing

1mo

Senior Principal ASIC Implementation Engineer

BAE Systems Multiple locations

ASIC Static Timing

1mo

CPU Physical Electrical Analysis Engineer, Santa Clara/Austin

Qualcomm Santa Clara, California

STA Place and Route

1mo

CPU Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

1mo

ASIC Design Engineer

Qualcomm San Diego, California

FPGA ASIC

1mo