STA Jobs in California

Physical Design Engineer Intern, BS - Summer 2027

Marvell Multiple locations

ASIC RTL

1mo

Physical Design Engineer Intern, MS - Summer 2027

Marvell Multiple locations

ASIC RTL

1mo

Principal Engineer, SOC Design

Samsung Semiconductor San Jose, California

ASIC RTL

1mo

CAD and PPA Methodology Engineer

Qualcomm San Diego, California

Verilog System Verilog

1mo

Physical Design Engineer (Engineer up to Principal Level)

Qualcomm Multiple locations

ASIC RTL

1mo

Sr. Memory Designer

Lattice Semiconductor San Jose, California

SystemVerilog FPGA

1mo

AI/ML driven ASIC Design and Implementation Automation Engineer

NXP Semiconductors San Diego, California

VHDL Verilog

1mo

Design Automation Engineer - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

1mo

Senior Static Timing Analysis (STA) Engineer

Intel Multiple locations

Logic Design Digital Design

1mo

CPU Server Physical Design Timing Engineer

Qualcomm Santa Clara, California

ASIC RTL

1mo

ASIC DTCO, Timing and Technology Engineer

Qualcomm San Diego, California

ASIC RTL

1mo

CPU Server Floorplan and Integration Engineer

Qualcomm Santa Clara, California

RTL STA

1mo

NoC Interconnect Design Engineer and Architect

Qualcomm San Diego, California

FPGA ASIC

1mo

Principal CPU Physical Design Engineer (San Diego, CA)

Qualcomm San Diego, California

ASIC RTL

1mo

Physical Design Engineer

Broadcom Multiple locations

RTL STA

1mo

R&D IC Design Engineer

Broadcom Multiple locations

VHDL Verilog

1mo

R&D IC Design Engineer

Broadcom Multiple locations

VHDL Verilog

1mo

Physical Design (Multiple levels)

Qualcomm San Diego, California

ASIC RTL

1mo

ASIC Methodology Engineer

Qualcomm Santa Clara, California

ASIC RTL

1mo

CPU STA CAD Engineer

Qualcomm Multiple locations

STA Static Timing

1mo