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CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) Intel Multiple locations Verilog System Verilog 1mo
Senior Technical Staff Engineer - Design Microchip Technology Bangalore, India SystemVerilog ASIC 1mo
Senior Technical Staff Engineer - Verification Microchip Technology Chandler, Arizona Verilog SystemVerilog 1mo
Senior Design Engineer - Mixed Signal IC Design Architect Microchip Technology United Kingdom - Whiteley Verilog SystemVerilog 1mo
Senior Technical Staff Engineer - Analog Design (SRAM Design) Microchip Technology San Jose, California Verilog FPGA 1mo
Senior Technical Staff Engineer – Architect (SoC) Microchip Technology Chandler, Arizona FPGA SOC 1mo
Technical Staff Engineer - AMS Verification Microchip Technology Chandler, Arizona SOC Verification 1mo
Director, Design Engineering – Data Center Solutions (DCS) Microchip Technology Bangalore, India Verilog SystemVerilog 1mo
Senior Technical Staff Engineer - Validation (System Design) Microchip Technology San Jose, California VHDL Verilog 1mo
Technical Staff Engineer - Design Implementation Microchip Technology Chandler, Arizona RTL Digital Design 1mo
Principal Engineer - Verification Microchip Technology Chennai, Tamil Nadu Verilog System Verilog 1mo
Principal Digital Verification Engineer Microchip Technology Bangalore, India Verilog System Verilog 1mo
Senior Technical Staff Engineer – Emulation Microchip Technology Multiple locations Verilog System Verilog 1mo