Aug. 17, 2026

ASIC Verification Engineer

HPE Juniper Networks Roseville, California

1mo

Aug. 16, 2026

Staff FPGA Design Engineer

Ursa Major Berthoud, Colorado

VHDL Verilog

1mo

Senior Embedded Software Engineer

Ursa Major Berthoud, Colorado

FPGA HDL

1mo

Senior Electrical Engineer

Ursa Major Longmont, Colorado

FPGA DFT

1mo

Avionics Design Manager

Ursa Major Longmont, Colorado

SystemVerilog FPGA

1mo

Senior Principal Engineer, Physical Design Engineering

Analog Devices Bangalore, India

RTL Digital Design

1mo

Physical Design Engineer

Syntiant Bengaluru, Karnataka

ASIC RTL

1mo

Digital Design Engineer

Syntiant San Diego, California

Verilog ASIC

1mo

Sr. FPGA Engineer II

Rocket Lab Long Beach, California

VHDL FPGA

1mo

Sr. FPGA Engineer I

Rocket Lab Long Beach, California

VHDL FPGA

1mo

FPGA Engineer II

Rocket Lab Long Beach, California

VHDL FPGA

1mo

Avionics Engineer - Design

Rocket Lab Auckland, Auckland Region

VHDL Verilog

1mo

Sr Staff Design Engineer

Lattice Semiconductor LPQ

FPGA ASIC

1mo

Applications Eng 3

Lattice Semiconductor Manila, Metro Manila

VHDL Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1mo

Sr Staff QA/Test Eng(RTL, FPGA backend tools)

Lattice Semiconductor Pune, Maharashtra

Verilog FPGA

1mo

Principal Engineer – CAD Design Engineering & EDA Infrastructure

Lattice Semiconductor San Jose, California

FPGA RTL

1mo

Silicon Validation Engineer

Lattice Semiconductor San Jose, California

VHDL Verilog

1mo

Staff Silicon Validation Engineer

Lattice Semiconductor San Jose, California

VHDL Verilog

1mo

Product Test Engineer

Lattice Semiconductor Hillsboro, Oregon

VHDL Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Manila, Metro Manila

SystemVerilog FPGA

1mo

Silicon Design Validation, Senior Manager

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Sr. Custom Circuit Design Engineer (Memory, FPGA Fabric Designer)

Lattice Semiconductor Pune, Maharashtra

FPGA Verification

1mo

Sr. Staff RTL Eng

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1mo

Staff Software Development Engineer(C++, EDA, Place and route)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Sr. Director, Humanoid / Robotics Strategic Marketing

Lattice Semiconductor San Jose, California

FPGA ASIC

1mo

Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

1mo

Integration Design Engineer

Lattice Semiconductor Penang, Malaysia

Verilog System Verilog

1mo

Senior Soft IP Design Engineer

Lattice Semiconductor Penang, Malaysia

Verilog SystemVerilog

1mo

Staff Applications Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Staff Applications Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Staff Field Applications Engineer

Lattice Semiconductor Taipei, Taipei

VHDL Verilog

1mo

SOC RTL Design Engineer

Lattice Semiconductor Pune, Maharashtra

Verilog System Verilog

1mo

Design Eng 4

Lattice Semiconductor Pune, Maharashtra

VHDL Verilog

1mo

Digital Eng (RTL, implementation)

Lattice Semiconductor Pune, Maharashtra

FPGA ASIC

1mo

Field Applications Engineer

Lattice Semiconductor Multiple locations

VHDL Verilog

1mo

Design Eng 2

Lattice Semiconductor Manila, Metro Manila

Verilog System Verilog

1mo

Senior Design Verification Engineer

Lattice Semiconductor Hyderabad, Telangana

SystemVerilog FPGA

1mo

Senior Staff IP Design Engineer

Lattice Semiconductor Penang, Malaysia

VHDL Verilog

1mo

Senior Applications Engineer – FPGA Tools

Lattice Semiconductor LSV

FPGA SOC

1mo

SOC Design Engineer

Lattice Semiconductor Shanghai, Shanghai

Verilog SystemVerilog

1mo

Legal Director, Commercial Transactions – Firmware

Lattice Semiconductor Multiple locations

FPGA SOC

1mo

Aug. 15, 2026

Sr Engineer I - Validation (Systems)

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Principal Engineer - Validation (Systems)

Microchip Technology Burnaby, British Columbia

VHDL Verilog

1mo

Technical Staff Engineer - Design

Microchip Technology Burnaby, British Columbia

Verilog System Verilog

1mo

Electronics Design Engineer

Silvus Technologies Los Angeles, California

FPGA Digital Design

1mo

Mixed Signal Electronic Design Engineer

Draper Cambridge, Massachusetts

VHDL Verilog

1mo

FC Verification Engineer

NVIDIA Yokneam, Israel

SOC Verification

1mo

SOC Verification Engineer

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Aug. 14, 2026

Principal Verification Engineer

Microchip Technology Dublin, Leinster

Verilog System Verilog

1mo