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Sept. 8, 2026
GPU DV Staff/Senior Staff Engineer
System FPGA Engineer
Network Processor IP Verification Sr Lead Engineer
Physical Design Engineer, Senior Staff - Hod Hasharon
CPU Physical Electrical Analysis Engineer, Santa Clara/Austin
CPU Physical Design Timing Engineer
SOC Power Design Engineer
Software Engineer, Senior
Firmware Engineer – SerDes PHY (all levels)
High-Speed Electrical and Optical Systems Validation Engineer - (all levels)
Digital Design Verification Engineer, Staff
Memory Designer
CAD RTL/DV Infrastructure Engineer, Staff
AI/ML Camera Lead Engineer
GPU Design Verification Engineer, Staff
NoC (RTL) Design-Sr Lead/Staff/Sr Staff
GPU Compiler Engineer - Cambridge, UK
Senior Staff Formal Verification Engineer
Graphics ASICS Hardware Design Engineer
System Performance Modeling Engineer
Pre-Silicon verification engineer
Entry Level Digital Design Engineer
Entry Level DFT Design Engineer
Digital Verification Intern - Summer 2027
Digital Design Intern - Summer 2027
SOC DFT Intern - Summer 2027
Digital Design Intern - Spring 2027
SOC DFT Intern - Spring 2027
Digital Design Intern - Summer 2027
Test Engineer (NPI Development)
Lead RTL Designer (PPA Experience)
Sept. 7, 2026
Camera Power Engineer
Senior Director Power Architecture, Datacenter AI
Computer/Data Science Staff Engineer for CAD - Cork, Ireland
Computer Science Senior Engineer for CAD - Cork, Ireland
Connectivity Project Engineer, Principal
CPU RTL Power Engineer (Senior/Lead/Staff)
Staff Engineer - DFT
CPU STA/Timing Engineer (Lead/Staff/Sr Staff)
CPU PDN & EM/IR Sign-Off Engineer (Lead/Staff)
Analog/Mixed Signal ASIC Design Engineer
SoC Systems & Infrastructure Engineer (Design • Validation • Debug • FPGA • Emulation • Software)
ASIC Design Engineer
Principal Physical Design Engineer - MCU
Principal HW/SW Co-Design
Junior Physical Design Engineer - MCU
Digital Verification Engineer - MCU
Sept. 6, 2026