SystemVerilog Jobs in Santa Clara, CA

Browse open SystemVerilog positions in Santa Clara, CA for FPGA, ASIC, and RTL engineers.

All Locations California 205 Texas 105 Austin, TX 91 Santa Clara, CA 70 Bangalore 60 Telangana 43 Hyderabad 43 Ontario 35

Senior ASIC Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

1d

Microarchitecture and Design Engineer - AI SoC

Intel Multiple locations

SystemVerilog RTL

2d

PhD Research Intern, AI Accelerator Design and VLSI - 2027

NVIDIA Santa Clara, California

SystemVerilog ASIC

3d

AI GPU Cache Designer

Intel Multiple locations

Verilog SystemVerilog

5d

ASIC Verification Engineer - New College Grad 2027

NVIDIA Multiple locations

SystemVerilog ASIC

5d

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Santa Clara, California

SystemVerilog FPGA

5d

Senior ASIC Design Verification Engineer - LPU

NVIDIA Multiple locations

SystemVerilog ASIC

11d

RF/Analog Design/Mixed-Signal Engineering Internship – Summer 2027

Qualcomm Multiple locations

Verilog SystemVerilog

15d

Senior Staff Digital Design Engineer

Marvell Multiple locations

SystemVerilog FPGA

16d

Custom SOC IP Verification Engineer

NVIDIA Multiple locations

SystemVerilog ASIC

17d

Midcore Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

17d

Front End Design Verification Engineer

Tenstorrent Santa Clara, California

SystemVerilog ASIC

18d

ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm Santa Clara, California

Verilog SystemVerilog

20d

Staff Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog ASIC

20d

Staff Design Verification Engineer – CPU Core Verification (Vector)

SiFive Multiple locations

SystemVerilog ASIC

20d

Staff Design Verification Engineer – CPU Core Verification (ALU)

SiFive Multiple locations

SystemVerilog ASIC

20d

Senior Design Verification Engineer – High Performance CPU Core

SiFive Multiple locations

SystemVerilog RTL

20d

Senior Design Verification Engineer – CPU Core Verification (Vector)

SiFive Multiple locations

SystemVerilog RTL

20d

Ph.D. Intern - Architecture, DSP & Systems Architecture

Marvell Multiple locations

Verilog SystemVerilog

22d

Design Verification Engineer

Intel Santa Clara, California

SystemVerilog FPGA

23d

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