SystemVerilog Jobs in Austin, TX
Browse open SystemVerilog positions in Austin, TX for FPGA, ASIC, and RTL engineers.
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California
210
Texas
109
Austin, TX
95
Santa Clara, CA
70
Bangalore
60
Telangana
43
Hyderabad
43
Ontario
36
Senior Design Verification Engineer
Digital Circuit Design Engineer
Design Verification Engineer
FPGA Design Engineer, Senior Principal
• AI/ML CAD Engineer, RTL & Design Verification
AI GPU Cache Designer
ASIC Verification Engineer - New College Grad 2027
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
FPGA Verification Engineer II
Senior ASIC Design Verification Engineer - LPU
Verification Designer
Custom SOC IP Verification Engineer
Staff Design Verification Engineer – Coherent Interconnect (CHI)
Staff Design Verification Engineer – High Performance CPU Core
Staff Design Verification Engineer – CPU Core Verification (Vector)
Staff Design Verification Engineer – CPU Core Verification (ALU)
Senior Design Verification Engineer – High Performance CPU Core
Senior Design Verification Engineer – CPU Core Verification (Vector)
Ph.D. Intern - Architecture, DSP & Systems Architecture
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