DFT Jobs in California

Silicon Design-for-Test (DFT) Engineer

MatX Multiple locations

Remote DFT Design for Test

2mo

ASIC/SOC Silicon Physical Design Engineer

MatX Multiple locations

Remote ASIC RTL

2mo

NVIDIA 2027 Internships: Hardware Design for Test (DFT)

NVIDIA Santa Clara, California

Digital Design STA

2mo

Director AI/ML Driven ASIC Design and Implementation Automation

NXP Semiconductors Multiple locations

VHDL Verilog

2mo

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

2mo

Principal Board Product Engineer

Marvell Multiple locations

ASIC Digital Design

2mo

Senior Principal Engineer – Hardware Chip Lead, Connectivity BU

Marvell Santa Clara, California

ASIC RTL

2mo

Lead ASIC Design Engineer

Broadcom San Jose, California

Verilog SystemVerilog

2mo

Senior Custom ASIC Engineering Lead

Broadcom Multiple locations

Verilog ASIC

2mo

Senior Custom ASIC Engineering Lead

Broadcom Multiple locations

Verilog ASIC

2mo

R&D Engineer IC Design 4

Broadcom Multiple locations

Verilog ASIC

2mo

R&D Engineer IC Design 4

Broadcom Multiple locations

Verilog ASIC

2mo

Senior Custom ASIC Engineering Lead

Broadcom San Jose, California

Verilog ASIC

2mo

DFT Lead Engineer

Broadcom San Jose, California

Verilog ASIC

2mo

Digital Design Engineer

Syntiant San Diego, California

Verilog ASIC

2mo

Principal Hardware Engineer

HPE Juniper Networks Sunnyvale, California

Verilog FPGA

2mo

Director, ASIC Design & Front-End Implementation

HPE Juniper Networks Roseville, California

Verilog SystemVerilog

2mo

Cell Modeling and Verification Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog SystemVerilog

2mo

Senior DFT - Silicon Validation Engineer

NVIDIA Santa Clara, California

RTL STA

2mo

Senior ASIC Floorplan Design Engineer

NVIDIA Multiple locations

ASIC Place and Route

2mo