July 22, 2026

Power Optimization Engineer

Etched Cupertino, California

ASIC RTL

3mo

Physical Design Engineer

Etched Cupertino, California

ASIC RTL

3mo

Performance Modeling Engineer

Etched Cupertino, California

ASIC RTL

3mo

Front-End Power Engineer

Etched Cupertino, California

Verilog SystemVerilog

3mo

Front-End CAD Engineer

Etched Cupertino, California

ASIC RTL

3mo

Emulation Software Engineer

Etched Cupertino, California

Verilog SystemVerilog

3mo

ASIC Timing Engineer

Etched Cupertino, California

ASIC RTL

3mo

FPGA Engineer

Astranis San Francisco, California

Verilog SystemVerilog

3mo

Hardware Engineer (FPGA/ASIC)

Jane Street New York City, New York

VHDL Verilog

3mo

ASIC Physical Design Engineer

Jane Street New York City, New York

ASIC RTL

3mo

ASIC Physical Design Engineer

Jane Street London, England

ASIC RTL

3mo

ASIC Engineer

Jane Street New York City, New York

FPGA ASIC

3mo

ASIC Engineer

Jane Street London, England

FPGA ASIC

3mo

Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic Multiple locations

FPGA ASIC

3mo

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Los Angeles, California

FPGA ASIC

3mo

Senior FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Irvine, California

FPGA ASIC

3mo

Senior Electronics Design Engineer

Silvus Technologies Los Angeles, California

FPGA Digital Design

3mo

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies Irvine, California

Verilog System Verilog

3mo

FPGA Design Engineer

Silvus Technologies Irvine, California

FPGA ASIC

3mo

FPGA Design Engineer

Silvus Technologies Los Angeles, California

FPGA ASIC

3mo

Verification Engineer

Tenstorrent Japan

Verilog System Verilog

3mo

Top Level Physical Design Engineer

Tenstorrent Multiple locations

RTL SOC

3mo

Technical Program Manager, Architecture

Tenstorrent Santa Clara, California

RTL DFT

3mo

Staff Engineer, CPU Core Verification

Tenstorrent Bengaluru, Karnataka

RTL UVM

3mo

Sr Staff Engineer, SoC RTL Design

Tenstorrent Toronto, Ontario

VHDL Verilog

3mo

Sr/Staff Engineer, Design Verification,System IP

Tenstorrent Bengaluru, Karnataka

SystemVerilog ASIC

3mo

Sr. Staff Engineer, RTL Physical Implementation Lead

Tenstorrent Multiple locations

VHDL Verilog

3mo

SOC Architect - Chiplet

Tenstorrent Munich, Bavaria

SOC Verification

3mo

Signal Integrity Engineer

Tenstorrent Multiple locations

ASIC Digital Design

3mo

Senior DFT Engineer, Architecture

Tenstorrent Tokyo, Tokyo

RTL Digital Design

3mo

Power Architect

Tenstorrent Toronto, Ontario

Verilog RTL

3mo

Physical Design Engineer - STA

Tenstorrent Multiple locations

RTL STA

3mo

Physical Design Engineer, PnR

Tenstorrent Multiple locations

RTL STA

3mo

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent Santa Clara, California

ASIC RTL

3mo

Physical Design Engineer

Tenstorrent Multiple locations

ASIC RTL

3mo

Full-Chip Physical Design Verification Engineer

Tenstorrent Multiple locations

RTL SOC

3mo

Fabric SOC Architect

Tenstorrent Santa Clara, California

SOC Verification

3mo

Engineering Program Manager, RISCV

Tenstorrent Austin, Texas

DFT SOC

3mo

Emulation Engineer, Automotive Robotics

Tenstorrent Munich, Bavaria

Verilog SystemVerilog

3mo

DFT Engineer, Automotive Robotics

Tenstorrent Munich, Bavaria

RTL DFT

3mo

DFT Engineer

Tenstorrent Santa Clara, California

RTL DFT

3mo

Design Verification Lead, AI Hardware

Tenstorrent Toronto, Ontario

SystemVerilog FPGA

3mo

CPU Verification Fellow, RISC-V High-Performance Processor

Tenstorrent Santa Clara, California

SystemVerilog FPGA

3mo

CPU Core Design Verification Test Generator Lead

Tenstorrent Multiple locations

Verification

3mo

CPU Core Design Verification Testbench Lead

Tenstorrent Multiple locations

RTL UVM

3mo

AI/ML Physical Design Flow Engineer

Tenstorrent Multiple locations

RTL STA

3mo

Software Verification Engineer

Baya Systems Bengaluru, Karnataka

SOC Verification

3mo

SOC-IP Architect

Baya Systems Cambridge, England

Place and Route SOC

3mo

Microarchitect and RTL Design Engineer

Baya Systems Cambridge, England

Verilog System Verilog

3mo

Microarchitect and RTL Design Engineer

Baya Systems Santa Clara, California

Verilog System Verilog

3mo