Verilog Jobs in Santa Clara, CA

Browse open Verilog positions in Santa Clara, CA for FPGA, ASIC, and RTL engineers.

All Locations California 410 Texas 188 Austin, TX 165 Santa Clara, CA 144 Bangalore 136 Telangana 81 Hyderabad 81 San Diego, CA 74

CPU Systems RTL Engineer

Qualcomm Multiple locations

VHDL Verilog

1mo

Design Verification Engineer — Memory Subsystem

Qualcomm Santa Clara, California

Verilog SystemVerilog

1mo

CPU RTL/AI Micro-Architect - AI Development

Qualcomm Multiple locations

VHDL Verilog

1mo

Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Tenstorrent Multiple locations

SystemVerilog UVM

1mo

Senior SRAM Engineer

NVIDIA Santa Clara, California

Verilog Static Timing

1mo

Senior Architecture Energy Modeling Engineer

NVIDIA Santa Clara, California

Verilog ASIC

1mo

Architecture Energy Modeling Engineer - New College Grad 2026

NVIDIA Santa Clara, California

Verilog ASIC

1mo

NVIDIA 2027 Internships: Mixed Signal Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware Verification

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware Engineering

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Hardware ASIC Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Digital Circuit Design

NVIDIA Santa Clara, California

VHDL Verilog

1mo

NVIDIA 2027 Internships: Computer Architecture

NVIDIA Santa Clara, California

VHDL Verilog

1mo

Staff Analog Design Engineer, SerDes Clocking

d-Matrix Multiple locations

Remote Verilog Synthesis

1mo

Senior Principal Digital IC Design Engineer

Marvell Santa Clara, California

Verilog SystemVerilog

1mo

Senior Staff Engineer, Firmware Engineering

Marvell Santa Clara, California

Verilog FPGA

1mo

Sr. Staff Design Verification Engineer

d-Matrix Multiple locations

Remote SystemVerilog ASIC

1mo

Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU

NVIDIA Multiple locations

Verilog SystemVerilog

1mo

Principal Design Verification Engineer – CPU Coherent Interconnect

SiFive Multiple locations

SystemVerilog ASIC

1mo

Senior ASIC Design Verification Engineer

Palo Alto Networks Santa Clara, California

SystemVerilog ASIC

1mo

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