DFT Jobs in Santa Clara, CA

Senior DFT Engineer

NVIDIA Multiple locations

RTL DFT

1mo

Senior System Integration and Validation Engineer

NVIDIA Santa Clara, California

Logic Design DFT

1mo

ASIC Design Engineer – Clocks IP

NVIDIA Multiple locations

Verilog ASIC

1mo

Physical Design CPU Methodology Engineer

Tenstorrent Santa Clara, California

ASIC RTL

1mo

CPU SRAM Design & Layout Engineer

Qualcomm Santa Clara, California

Verilog Static Timing

1mo

Design for Test Intern, BS - Summer 2027

Marvell Multiple locations

UVM DFT

1mo

Lead CPU Firmware Verification and Validation Engineer/ Manager

Qualcomm Santa Clara, California

DFT Design for Test

1mo

Silicon Hardware Engineering - Intern, Graduate

Intel Multiple locations

Logic Design DFT

1mo

Silicon Hardware Engineering - Intern, Bachelor’s

Intel Multiple locations

Logic Design DFT

1mo

CPU DFT Engineer

Qualcomm Santa Clara, California

VHDL Verilog

1mo

Physical Design Engineer (Engineer up to Principal Level)

Qualcomm Multiple locations

ASIC RTL

1mo

CPU-Core RTL Director

Qualcomm Multiple locations

SystemVerilog RTL

1mo

Product Development/DFX Lead - Neuromorphic Computing

Intel Multiple locations

Verilog System Verilog

1mo

Senior Static Timing Analysis (STA) Engineer

Intel Multiple locations

Logic Design Digital Design

1mo

ASIC Design Engineer (Hardware Security)

Qualcomm Multiple locations

Verilog System Verilog

1mo

System Level Product Development Engineer

NVIDIA Santa Clara, California

ASIC DFT

1mo

Product Development Engineer -- Post-Si Characterization

NVIDIA Santa Clara, California

ASIC Digital Design

1mo

Characterization Product Development Engineer

NVIDIA Santa Clara, California

ASIC Digital Design

1mo

NVIDIA 2027 Internships: Hardware Design for Test (DFT)

NVIDIA Santa Clara, California

Digital Design STA

2mo

Senior DFT Engineer

NVIDIA Santa Clara, California

ASIC RTL

2mo