Staff DV Engineer
E-Space
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Claim and feature this jobHDL & Verification Methodology
· Strong proficiency in Verilog and SystemVerilog
· Experience writing tests within an existing UVM verification environment
· Solid understanding of UVM architecture and methodology
Programming & Scripting
· Ability to write C/C++ code for verification purposes
· Some scripting experience in Perl or Python
Verification Planning & Execution
· Ability to contribute to and help write test plans
· Experience writing and maintaining verification tests
· Ability to debug RTL simulations independently
Leadership
· Experience leading design verification efforts at the block level
· Experience driving code coverage closure on assigned blocks
6+ years of design verification experience in the semiconductor industry
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