Principal ASIC Design Engineer - Chip Lead

CesiumAstro logo

CesiumAstro

Aliso Viejo , California , United States
Verilog System Verilog ASIC RTL UVM OVM STA Synthesis DFT Verification
Apply Now Posted today Please mention FPGAjobs in your application — it helps a lot!

Hiring for this role?

Claim and feature it — priority homepage placement, your logo, and a slot in the jobs newsletter.

Claim and feature this job

Get weekly updates from CesiumAstro

We'll email a link to confirm first, and every message has a one-click unsubscribe. Filter by skill, location, or frequency · internships, entry-level, or blog posts.

Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.

This position is with Jariet Technologies, Inc., a subsidiary of CesiumAstro. Jariet is developing breakthrough technologies to permit digital communications technology to be applied at micro/mm-Wave speeds using standard CMOS processes. Jariet is well positioned to provide ASIC products into emerging markets in multi-antenna beamforming communications systems and wireless infrastructure as well as digital deployments into microwave point-to-point links and radar systems. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team.


We are looking to add a Principal ASIC Design Engineer - Chip Lead for our next generation industry leading high speed mixed signal/DSP projects. We are specifically looking for someone with cradle-to-grave experience who knows all levels of large, high-speed communications chip design. The ideal candidate will have knowledge in all or most of the following areas: digital communications systems, DSP, ASIC microacrchitecture, analog IP integration, embedded processors, high level verification, RTL design with multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring up, debug, lab testing, and transitioning a product from first sample through release to volume production.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS
  • Master’s in Engineering with a minimum of 10 years of experience. 
  • Experience with the IC/ASIC development flow from concept through production release of silicon.
  • Experience in defining and using advanced front-end design flows from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team.
  • Experience in high speed analog block integration into digital logic.
  • The candidate must have a well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements.
  • Excellent program management, people management, and project tracking skills.
  • Experience with customer communications and marketing/sales interactions.
  • Experience with ASIC verification using random constraint coverage driven verification methodology like UVM, VMM, OVM or SPECMAN.
  • Fluency with Verilog and System Verilog, experience with synthesis, formal verification, and STA flow set up. Experience with low power design flows highly desirable.
  • Experience in DSP block implementation highly desirable.

    • Related openings